First Experimental Ge CMOS FinFETs Directly on SOI Substrate

Abstract

High-performance Ge CMOS FinFETs directly on thin silicon on insulator (SOI) wafer are demonstrated. For the first time, NFET of L-channel = 120nm and Fin width=40nm with high I-on/I-off ratio (>10(5)), excellent drain induced barrier lowering (DIBL) (110mV/V) and subthreshold swing (S. S) (144mV/dec) has been shown. Both Ge n- and p-channel FinFETs with multi-fins have been achieved. Even the NFET of L-channel =90nm exhibits a pretty well on-off behavior after forming gas annealing.