First Experimental Ge CMOS FinFETs Directly on SOI Substrate

dc.contributor.author	Chung, Cheng-Ting	en_US
dc.contributor.author	Chen, Che-Wei	en_US
dc.contributor.author	Lin, Jyun-Chih	en_US
dc.contributor.author	Wu, Che-Chen	en_US
dc.contributor.author	Chien, Chao-Hsin	en_US
dc.contributor.author	Luo, Guang-Li	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2014-12-08T15:30:46Z
dc.date.available	2014-12-08T15:30:46Z
dc.date.issued	2012	en_US
dc.description.abstract	High-performance Ge CMOS FinFETs directly on thin silicon on insulator (SOI) wafer are demonstrated. For the first time, NFET of L-channel = 120nm and Fin width=40nm with high I-on/I-off ratio (>10(5)), excellent drain induced barrier lowering (DIBL) (110mV/V) and subthreshold swing (S. S) (144mV/dec) has been shown. Both Ge n- and p-channel FinFETs with multi-fins have been achieved. Even the NFET of L-channel =90nm exhibits a pretty well on-off behavior after forming gas annealing.	en_US
dc.identifier.isbn	978-1-4673-4870-6	en_US
dc.identifier.journal	2012 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/21983
dc.identifier.wosnumber	WOS:000320615600097
dc.language.iso	en_US	en_US
dc.title	First Experimental Ge CMOS FinFETs Directly on SOI Substrate	en_US
dc.type	Proceedings Paper	en_US

Files

Now showing 1 - 1 of 1