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Browsing by Author "Wu, Chun-Shen"

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    Research of Electroplating and Electroless Plating for Low Temperature Bonding in 3D Heterogeneous Integration
    (2014)
    Hu, Yu-Chen
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    Chang, Yao-Jen
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    Wu, Chun-Shen
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    Cheng, Yung Mao
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    Chen, Wei Jen
    In this paper, a 3D chip-to-chip hetero-integration scheme without Si interposer is demonstrated under 270 degrees C thermal budget. The scheme successfully integrates advanced and common technology node logic chips by Cu/Sn to ENIG bumping. Cu/Sn mu-bumps are electroplated on common technology node and ENIG joints are electroless-plated on advanced technology node opening pads, respectively. Herein, 60 mu m bump pitch, 40 mu m diameter of Cu/Sn mu-bump and 50 mu m diameter of ENIG are presented. Without cracks and voids, the 3D C2C scheme gives an efficient approach for future development of 3D IC.