Browsing by Author "Wu, Chung-Yu"

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45-nm Planar Bulk-CMOS 23-GHz LNAs With High-Q Above-IC Inductors
(2010)
Wang, Wen-Chieh
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Huang, Zue-Der
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Carchon, Geert
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Mercha, Abdelkarim
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Decoutere, Stefaan
Two 23 GHz low-noise amplifier (LNA) have been designed and implemented by 45 nm planar bulk-CMOS technology with high-Q above-IC inductors. In the designed LNAs, the structure of cascode amplifier with source inductive degeneration is used. All high-Q above-IC inductors have been implemented by thin-film wafer-level packaging (WLP) technology. The fabricated one-stage LNA has a good linearity where the input 1 dB compression point (IP(-1dB)) is -9.5 dBm and the input referred third-order intercept point (P(IIP3)) is +2.25 dBm. It is operated with a 1 V power supply drawing a current of only 3.6 mA. The fabricated one-stage LNA has demonstrated a 4 dB noise figure (NF) and a 7.1 dB gain at the peak gain frequency of 23 GHz. Moreover, the fabricated two-stage LNA has the IP(-1dB) of -16 dBm and the P(IIP3) of -4.2 dBm. It drains 9.3 mA from 1-V power supply. This two-stage LNA has demonstrated a 4.4 dB NF and a 11.6 dB gain at the peak gain frequency of 23.4 GHz. The fabricated one-stage LNA has the highest figure-of-merit (FOM). The experimental results have proved the suitability of 45 nm gate length planar bulk-CMOS devices for RF ICs above 20 GHz.
A 1 V 23 GHz Low-Noise Amplifier in 45 nm Planar Bulk-CMOS Technology With High-Q Above-IC Inductors
(2009-05-01)
Wang, Wen-Chieh
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Huang, Zue-Der
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Carchon, Geert
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Mercha, Abdelkarim
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Decoutere, Stefaan
A 23 GHz electrostatic discharge-protected low-noise amplifier (LNA) has been designed and implemented by 45 nm planar bulk-CMOS technology with high-Q above-IC inductors. In the designed LNA, the structure of a one-stage cascode amplifier with source inductive degeneration is used. All high-Q above-IC inductors have been implemented by thin-film wafer-level packaging technology. The fabricated LNA has a good linearity where the input I dB compression point (IP(-1) (dB))is - 9.5 dBm and the input referred third-order intercept point (P(IIP3)) is +2.25 dBm. It is-operated with a I V power supply drawing a current of only 3.6 mA. The fabricated LNA has demonstrated a 4 dB noise figure and a 7.1 dB gain at the peak gain frequency of 23 GHz, and it has the highest figure-of-merit. The experimental results have proved the suitability of 45 nm gate length bulk-CMOS devices for PF ICs above 20 GHz.
A 1-V RF-CMOS LNA design utilizing the technique of capacitive feedback matching network
(2009-01-01)
Shahroury, Fadi Riad
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Wu, Chung-Yu
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a CMOS low-noise amplifier (LNA) with a new input matching topology has been proposed, analyzed and measured. The input matching network is designed through the technique of capacitive feedback matching network. The proposed LNA which is implemented in a 0.18-mu m 1P6M CMOS technology is operated at the frequency of 12.8 GHz. It has a gain S21 of 13.2 dB, a noise figure (NF) of 4.57 dB and an NF(min) of 4.46 dB. The reverse isolation S12 of the LNA can achieve -40dB and the input and output return losses are better than -11 dB. The input 1-dB compression point is -11 dB m and IIP3 is -0.5 dB m. This LNA drains 10 mA from the supply voltage of 1 V. (C) 2008 Published by Elsevier B.V.
A 1.5-V 3 similar to 10-GHz 0.18-mu m CMOS Frequency Synthesizer for MB-OFDM UWB Applications
(2008)
Huang, Zue-Der
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Kuo, Fong-Wei
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Wang, Wen-Chieh
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Wu, Chung-Yu
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電子工程學系及電子研究所
An Ultra wide band (UWB) frequency synthesizer is designed and fabricated in 0.18-mu m CMOS technology to generate all the carrier frequencies for 13 bands distributed from 3 to 10 GHz. It is composed of one phase-locked loop (PLL) and three single-side band (SSB) mixers. The polyphase filter is used to generate all needed quadrature signals in the circuit and band selectors are to select the frequency band. The sideband rejection can be over 30dB. The switching time between bands is around 3.75ns. The current consumption is 72mA under 1.5-V power supply.
A 13.56 MHz 40 mW CMOS High-Efficiency Inductive Link Power Supply Utilizing On-Chip Delay-Compensated Voltage Doubler Rectifier and Multiple LDOs for Implantable Medical Devices
(2014-11-01)
Wu, Chung-Yu
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Qian, Xin-Hong
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Cheng, Ming-Seng
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Liang, Yu-An
;
Chen, Wei-Ming
In this paper, a 13.56 MHz CMOS near-field inductive link power supply (ILPS) that can deliver 20 mA output current for implantable medical devices (IMDs) is proposed and fabricated. In the proposed ILPS, the pair of inductive link coils is constructed in the spiral shape with a ferrite core to save space and increase efficiency. Experimental results have shown that the near-field coils can transmit power at the resonant frequency of 13.56 MHz with the transmission efficiency up to 76.3%. The CMOS power regulator is composed of active voltage doubler rectifier (VD) and low-dropout regulators (LDOs). In the active VD with the comparator, the input offset voltage is adjustable for delay compensation and a start-up control circuit is added to achieve robust start-up mechanism. On-chip delay compensation control with SR-latches is proposed to prevent from error glitch switching on offset voltage control and achieve accurate delay compensation so that the reverse current conduction can be avoided and the efficiency can be increased. Three fully-integrated LDOs with rectifier output voltage of 2 V to 1.8 V are realized for analog (ALDO), digital (DLDO), and reference-voltage (RLDO) circuits. Thus the performance of individual LDO can be optimized. The measured output ripple voltage of the active VD is 10.4 mV. The power conversion efficiency (PCE) is 85% under 20 mA output current. The measured dropout voltage is 384 mV. As compared with other designs, the proposed ILPS has lower ripple voltages, lower dropout voltage, and higher PCE.
A 13.56 MHZ METAMATERIAL FOR THE WIRELESS POWER TRANSMISSION ENHANCEMENT IN IMPLANTABLE BIOMEDICAL DEVICES
(2019-01-01)
Chen, Kuan-Jung
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Chen, Wei-Ming
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Tan, Li-Yang
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Cheng, Yu-Ting
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Ker, Ming-Dou
This paper presents a 13.56MHz metamaterial for wireless power transmission (WPT) enhancement in implantable biomedical devices based on the evanescent wave coupling mechanism. The power transmission efficiency (PTE) will increase from 46 to 51% with the metamaterial while the transmitting and receiving antennas are placed with a 1 cm distance and lcm offset horizontal misalignment, will increase from 39 to 46% with the metamaterial while the two antenna planes are placed at a distance of 1.5 cm with an axial offset of 15, and will increase from 28 to 50% with two pieces of metamaterial placed with a 0.5cm distance while the two antenna planes are placed with a 1.5 cm distance and 1 cm offset horizontal misalignment.
A 16-Channel CMOS Chopper-Stabilized Analog Front-End Acquisition Circuits for ECoG Detection
(2017-01-01)
Cheng, Cheng-Hsiang
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Chen, Zhi-Xin
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Wu, Chung-Yu
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電子工程學系及電子研究所
;
生醫電子轉譯研究中心
In this paper, a 16-channel analog front-end (AFE) ECoG-signal acquisition circuit for closed-loop seizure control system is presented. It is composed of 16 auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIA) with band-pass filters, 16 programmable transconductance-gain amplifiers, a multiplexer, a transimpedance amplifier, and a 10-bit SAR ADC. The low input-referred noise is achieved by using chopper modulation technique in AR-CSCCIA. To reduce the undesired effects of chopper modulation, an improved offset reduction loop (ORL) is proposed to reduce output offset generated by input chopper mismatches. The digital ripple reduction loop (RRL) is also used to reduce chopper ripple. Moreover, to prevent from overstress in MOS devices caused by high stimulation voltage, an input protection circuit with high-voltage-tolerant switches is proposed to make the AFE amplifiers sharing the same electrode with high voltage stimulators. The fabricated AFE acquisition circuit has 49.1/59.1/67.9 dB programmable gain and 2.09uV(rms) input referred noise in a bandwidth 0.5-100 Hz. The measured power consumption of AFE is 3.26 uW per channel and the noise efficiency factor (NEF) is 3.78.
A 16-Channel CMOS Chopper-Stabilized Analog Front-End ECoG Acquisition Circuit for a Closed-Loop Epileptic Seizure Control System
(2018-06-01)
Wu, Chung-Yu
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Cheng, Cheng-Hsiang
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Chen, Zhi-Xin
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電子工程學系及電子研究所
;
生醫電子轉譯研究中心
In this paper, a 16-channel analog front-end (AFE) electrocorticography signal acquisition circuit for a closed-loop seizure control system is presented. It is composed of 16 input protection circuits, 16 auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIA) with bandpass filters, 16 programmable transconductance gain amplifiers, a multiplexer, a transimpedance amplifier, and a 128-kS/s 10-bit delta-modulated successive-approximation-register analog-todigital converter (SAR ADC). In closed-loop seizure control system applications, the stimulator shares the same electrode with the AFE amplifier for effective suppression of epileptic seizures. To prevent from overstress in MOS devices caused by high stimulation voltage, an input protection circuit with a high-voltage-tolerant switch is proposed for the AFE amplifier. Moreover, low input-referred noise is achieved by using the chopper modulation technique in the AR-CSCCIA. To reduce the undesired effects of chopper modulation, an improved offset reduction loop is proposed to reduce the output offset generated by input chopper mismatches. The digital ripple reduction loop is also used to reduce the chopper ripple. The fabricated AFE amplifier has 49.1-/59.4-/67.9-dB programmable gain and 2.02-mu Vrms input referred noise in a bandwidth of 0.59-117 Hz. The measured power consumption of the AFE amplifier is 3.26 mu W per channel, and the noise efficiency factor is 3.36. The in vivo animal test has been successfully performed to verify the functions. It is shown that the proposed AFE acquisition circuit is suitable for implantable closed-loop seizure control systems.
A 2.36 mu W/Ch CMOS 8-Channel EEG Acquisition Unit with Input Protection Circuits for Applications Under Transcranial Direct Current Stimulation
(2019-01-01)
Wu, Chung-Yu
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Huang, Chi-Wei
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Tsai, Tzung-Lin
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A 0.18um-CMOS 8-channel EEG acquisition unit with input protection circuits is designed and fabricated for EEG monitoring under the transcranial direct current stimulation (tDCS). The capacitively-coupled chopper instrumentation amplifier (CCCIA) with chopper modulation is used to suppress flicker noise and amplify input EEG signals. To filter out high frequency noise with high linearity, the switched-capacitor low-pass filter (SC-LPF) is proposed. The switchedcapacitor amplifier (SC-Amp) is also proposed to drive ADC capacitor array. The input protection circuit (IPC) is implemented by I/O device to keep internal circuits from overstress and artifacts from the tDCS. A 10-bit SAR ADC with offset-calibration comparator is integrated for accurate ADC conversion. The fabricated EEG acquisition unit has programmable gain 57.5/67.6/78.5dB. The measured power dissipation of a single CCCIA circuit is 2.36 mu W per channel. The measured recovery time is 7.5ms after the tDCS stimulation. It has been verified that the designed chip can record real EEG signals.
A 24-GHz CMOS current-mode power amplifier with high PAE and output power
(2007)
Wu, Chung-Yu
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Hsu, Shun-Wei
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Wang, Wen-Chieh
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A new 24-GHz CMOS current-mode power amplifier in 0.13-mu m CMOS technology is proposed. By using the two-stage cascade current-mirror structure, the power amplifier has a maximum output power of 17.8 dBm, the 0P(1dB) of 13.8 dBm and the power gain of 23 dB under the supply voltage of 1.2V and the total power dissipation of 239 mW. As compared to other PAs at 17 similar to 24 GHz the proposed current-mode PA has the highest power added efficiency (PAE) of 34.6% and the largest output power.
A 3-10 GHz CMOS UWB Low-Noise Amplifier With ESD Protection Circuits
(2009-11-01)
Wu, Chung-Yu
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Lo, Yi-Kai
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Chen, Min-Chiao
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A low-power fully integrated low-noise amplifier (LNA) with an on-chip electrostatic-static discharge (ESD) protection circuit for ultra-wide band (UWB) applications is presented. With the use of a common-gate scheme with a g(m)-boosted technique, a simple input matching network, low noise figure (NF), and low power consumption can be achieved. Through the combination of an input matching network, an ESD clamp circuit has been designed for the proposed LNA circuit to enhance system robustness. The measured results show that the fabricated LNA can be operated over the full UWB bandwidth of 3.0 to 10.35 GHz. The input return loss (S(11)) and output return loss (S(22)) are less than -8.3 dB and -9 dB, respectively. The measured power gain (S(21)) is 11 +/- 1.5 dB, and the measured minimum NF is 3.3 dB at 4 GHz. The dc power dissipation is 7.2 mW from a 1.2 V supply. The chip area, including testing pads, is 1.05 mm x 0.73 mm.
A 3.1 similar to 10.6 GHz CMOS direct-conversion receiver for UWB applications
(2006)
Wu, Chung-Yu
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Lo, Yi-Kai
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Chen, Min-Chiao
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, a 3.1 similar to 10.6 GHz fully integrated low-power CMOS direct-conversion receiver for ultra-wideband (UWB) applications is proposed and analyzed. The proposed receiver consists of a wideband low-noise amplifier (WLNA), quadrature down-conversion mixers, output I/Q buffers and a carrier generator. This chip was designed in 0.13-um CMOS technology. According to the simulation results, the proposed receiver has noise figure (NF) of 4.1 similar to 7.1 dB, receiver voltage gain of 22 dB, and input-referred 1-dB compression point (P-1dB) of -22 similar to-26 dBm and third-order intercept point (IIP3) of -12 similar to-16 dBm. It consumes 38.4 mW from 1.2 V power supply.
A 60-GHz, 14% Tuning Range, Multi-Band VCO with a Single Variable Inductor
(2008)
Yu, Chi-Yao
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Chen, Wei-Zen
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Wu, Chung-Yu
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Lu, Tai-You
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電子工程學系及電子研究所
This paper presents the design of a 60-GHz, 14% tuning range VCO with a single variable inductor (VID). By employing the proposed frequency tuning scheme, wide-tuning range as well as multi-band operations are achieved without sacrificing its operating frequency. Fabricated in a 90-nm CMOS process, the VCO is capable of covering frequency range from 53.1 to 61.3 GHz. The measured phase noise from a 61.3 GHz carrier is about -118.75 dBc/Hz at 10-MHz offset, and the output power is -6.6 dBm. The VCO core dissipates 8.7 mW from a 0.7-V supply. Chip size is 0.28 x 0.36 mm(2).
A 65nm CMOS Low-Power MedRadio-band Integer-N Cascaded Phase-Locked Loop for Implantable Medical Systems
(2014-01-01)
Wang, Yi-Xiao
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Chen, Wei-Ming
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Wu, Chung-Yu
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電機學院
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College of Electrical and Computer Engineering
This paper presents a low-power MedRadio-band integer-N phase-locked Loop (PLL) system which is composed of two charge-pump PLLs cascade connected. The PLL provides the operation clock and local carrier signals for an implantable medical electronic system. In addition, to avoid the off-chip crystal oscillator, the 13.56 MHz Industrial, Scientific and Medical (ISM) band signal from the wireless power transmission system is adopted as the input reference signal for the PLL. Ring-based voltage controlled oscillators (VCOs) with current control units are adopted to reduce chip area and power dissipation. The proposed cascaded PLL system is designed and implemented in TSMC 65-nm CMOS technology. The measured jitter for 216.96 MHz signal is 12.23 ps and the phase noise is -65.9 dBc/Hz at 100 kHz frequency offset under 402.926 MHz carrier frequency. The measured power dissipations are 66 mu W in the first PLL and 195 mu W in the whole system under 1-V supply voltage. The chip area is 0.1088 mm(2) and no off-chip component is required which is suitable for the integration of the implantable medical electronic system.
A 78 similar to 102 GHz Front-End Receiver in 90 nm CMOS Technology
(2011-09-01)
Su, Hsuan-Yi
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Hu, Robert
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Wu, Chung-Yu
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this letter, a 78 similar to 102 GHz front-end receiver designed in 90 nm CMOS technology is presented. It consists of an ultra-wideband low-noise amplifier, a subharmonic mixer, and an IF buffer. This receiver has a peak gain of 11.8 dB at 94 GHz with the noise figure of 13.4 dB. The measured input-referred 1 dB compression point is -14.5 dBm and the total power dissipation is 18.6 mW. The chip size is 680 x 1020 mu m(2).
A Bone-Guided Cochlear Implant CMOS Microsystem Preserving Acoustic Hearing
(2017-01-01)
Qian, Xin-Hong
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Wu, Yi-Chung
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Yang, Tzu-Yi
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Cheng, Cheng-Hsiang
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Chu, Hsing-Chien
In this paper, a bone-guided cochlear implant (BGCI) SOC microsystem is proposed and designed. The BGCI microsystem uses four or more electrodes placed on the bone surface of the cochlea and one on the round window to preserve partially the acoustic hearing. The external SOC of the BGCI processes the acoustic signals and generates stimulation patterns and command that are transmitted to the implanted chip through the 13.56MHz wireless power and bidirectional data telemetry. The implanted chip with 4-channel high-voltage-tolerant stimulator generates biphasic stimulation currents up to 800 mu A and sends back the power indication and electrode impedance error signals to the external SOC. Electrical tests on the fabricated BGCI has been performed. The in-vivo animal tests on guinea pigs has shown the evoked Wave III of EABR waveforms. The proposed BGCI can be applied to patients with high-frequency hearing loss, tinnitus, and dizziness.
A CMOS 13.56-MHz High-Efficiency Low-Dropout-Voltage 40-mW Inductive Link Power Supply Utilizing On-Chip Delay-Compensated Voltage Doubler Rectifier and Multiple LDOs for Implantable Medical Devices
(2013)
Qian, Xin-Hong
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Cheng, Ming-Seng
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Wu, Chung-Yu
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電子物理學系
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Department of Electrophysics
A near-field 13.56-MHz 20mA inductive energy transmission device with ferrite core spiral coils and CMOS power regulator is designed and tested. The power regulator is composed of active voltage doubler (VD) rectifier and low-dropout regulators (LDOs). In order to avoid large space requirement of coil and further increase its efficiency in the implantable medical devices (IMDs), the coils are constructed in the spiral shape with a ferrite core. In the VD with the comparator, the input offset voltage is adjustable for delay compensation and a start-up control circuit is added to achieve robust start-up mechanism. On-chip delay compensation control is implemented to prevent from reverse current conduction and increase the efficiency. Three fully-integrated LDOs with rectifier output voltage of 2V to 1.8V are realized: LDO for analog circuits (ALDO), LDO for digital circuits (DLDO) and LDO for reference-voltage circuits (RLDO). Thus the performance of individual LDO can be optimized. Both ALDO and RLDO have low crosstalk noise from DLDO. The measured ripple voltage of rectifier output is 10.4mV. The power conversion efficiency (PCE) of 85% with 20mA output current. The measured dropout voltage is 384mV. As compared with other designs, the proposed Inductive link power supply has lower ripple voltages and dropout voltage, and higher PCE.
A CMOS 256-pixel Photovoltaics-powered Implantable Chip with Active Pixel Sensors and Iridium-oxide Electrodes for Subretinal Prostheses
(2018-01-01)
Wu, Chung-Yu
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Kuo, Po-Han
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Lin, Po-Kang
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Chen, Po-Chun
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Sung, Wei-Jie
A CMOS implantable chip with 256 active pixel sensors (APSs), on-chip photovoltaic cells, and iridium-oxide (IrOx) electrodes is proposed and designed for subretinal prostheses. In the proposed chip, the on-chip electrode surface is deposited with IrOx by RF sputtering and photolithography patterning. The divisional power supply scheme (DPSS) is adopted to generate sufficient stimulation current whereas the APS is used to enhance the image sensitivity. The proposed chip consists of a 16 x 16 photodiode array with 8 DPSS divisions, control signal generator circuits, and photovoltaic cells. It is designed and fabricated into 180 nm CMOS image sensor (CIS) technology and postprocessed with an IrOx coating. From the electrical measurement results, the fabricated chip has a peak output stimulation current of 16.7 mu A under the equivalent electrode impedance load. The stimulation frequency is 30.2 Hz and the amount of injected charges at each pixel is 3.5 nC. Both image light sensitivity and injection charges are significantly improved. The surface morphology, crystallinity, charge storage capacity, and biocompatibility of sputtering iridium oxide film (SIROF) were investigated. As a result, the SIROF has desirable physical and electrochemical properties that make it suitable for the neurostimulation electrodes on the 256-pixel implantable chip. The 7-month biocompatibility and charge delivery capability of the fabricated chip have been confirmed by electroretinography (ERG) measurement on a Lanyu minipig in in vivo animal tests.
A CMOS 256-Pixel Self-Photovoltaics-Powered Subretinal Prosthetic Chip with Wide Image Dynamic Range and Shared Electrodes and Its In Vitro Experimental Results on Rd1 Mice
(2019-01-01)
Wu, Chung-Yu
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Tzeng, Chi-Kuan
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Huang, Shih-Yun
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Chu, Fang-Liang
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Chiao, Chuan-Chin
A self-photovoltaics-powered CMOS 256-pixel implantable chip with wide image dynamic range and shared electrodes is proposed and fabricated for subretinal prostheses. The infra-red (IR) light is incident only on photovoltaic cells of the chip whereas the visible light is mainly incident on pixels. The proposed adaptive background cancellation circuit (ABCC) is adopted to increase the image dynamic range so that the subretinal chip can adapt for different surrounding illuminances. Moreover, the bi-directional sharing electrodes (BDSEs) is used to increase electrode size under the same chip area and boost the stimulation charges to 11.4 nC. The functions of the chip have been successfully validated with both electrical measurement and in vitro patch clamp experiments with the retinas of Rd1 mice.
A CMOS Bio-Inspired 2-D Motion Direction Sensor Based on a Direction Computation Method Derived From the Directionally Selective Ganglion Cells in the Retina
(2011-12-01)
Yang, Wen-Chia
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Lin, Li-Ju
;
Chiueh, Herming
;
Wu, Chung-Yu
;
電子工程學系及電子研究所
A CMOS bio-inspired motion direction sensor structure and its associated computation method are proposed. Both method and structure with excitation-inhibition operation are derived from the directionally selective ganglion cells (DSGCs) in the retina to mimic their functions. Edge-number normalization for direction calculation and pseudo-random tessellation (PRT) structure for pixel layout arrangement are also proposed to enhance the accuracy of the computation. An experimental chip based on the proposed method and structure has been designed, fabricated, and measured. The chip comprised 32 x 32 pixels with a pixel size of 63 x 63 mu m(2) and a fill factor of 12.8%. The total chip size is 3.3 x 4.2 mm(2) and the power consumption is 9.9 mW in the dark and 21 mW at a maximum clock rate of 10 MHz with 3.3-V power supply. The fabricated chip has been measured with different moving patterns, and a computation error of less than 11 degrees has been accomplished. This verifies the correct functions of the proposed motion direction sensor. With the capability of real-time motion detection and processing under low power dissipation, the proposed sensor is feasible for many applications.