A 1-V RF-CMOS LNA design utilizing the technique of capacitive feedback matching network

Abstract

In this paper, a CMOS low-noise amplifier (LNA) with a new input matching topology has been proposed, analyzed and measured. The input matching network is designed through the technique of capacitive feedback matching network. The proposed LNA which is implemented in a 0.18-mu m 1P6M CMOS technology is operated at the frequency of 12.8 GHz. It has a gain S21 of 13.2 dB, a noise figure (NF) of 4.57 dB and an NF(min) of 4.46 dB. The reverse isolation S12 of the LNA can achieve -40dB and the input and output return losses are better than -11 dB. The input 1-dB compression point is -11 dB m and IIP3 is -0.5 dB m. This LNA drains 10 mA from the supply voltage of 1 V. (C) 2008 Published by Elsevier B.V.