Browsing by Author "Wu, Hui-I"

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A 1-V, Low-Power CMOS LNA for Ultra-wideband Receivers
(2007)
Chang, Po Yang
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Wu, Hui-I
;
Jou, Christina F.
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電信工程研究所
;
Institute of Communications Engineering
A 1-V, low-power ultra-wideband (UWB) low-noise amplifier (LNA) for IEEE 802.153a is implemented in TSMC 0.18-mu m. mixed signal/RF CMOS process. With only 1V bias voltage, the LNA can achieve a measured flat power gain (S21) of 10dB from 2.5 to 8.5 GHz while consuming only 7.25 mW. The minimum noise figure is 3.46dB. A simplified Chebyshev filter is used to achieve an input broadband matching of a measured S11 < -7.1dB from 3.1 to 10.6 GHz. An output-matching buffer is designed specially to match for high gain at upper frequency, the measured S22 is <-12.5dB from 3.1 GHz to 10.6 GHz. Furthermore, the high frequency electromagnetic effect of the transmission lines is considered in this circuit.
A 10 similar to 18GHz wide-band transfonner feedback LNA
(2007)
Chiang, Pei-Yuan
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Jou, Christina. F.
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Wu, Hui-I
;
Huang, Zhe-Yang
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傳播研究所
A wide-band (10 similar to 18GHz) low noise amplifier(LNA) is presented. With transformer feedback in the traditional cascode amplifier, good input matching is achieved from 10 GHz to 18 GHz. The noise figure is below 3.5dB over 10-18GHz. There is no input-matching elements in the input gate of the cascode amplifier, so that the LNA can achieve lower NF. The LNA is designed based on CMOS TSMC 0.18 mu m mixed signal/RF process. With 1.8V supply voltage and three stage amplifiers to achieve wider gain bandwidth, the LNA can achieve input-matching of -12dB over the bandwidth; minimum NIT 2.4dB; gain(S21) of 17dB and 1dB gain compression(P1dB) at -22.6dB. The power consumption is 37.6mW(exclude buffer).
A 3-8 GHz RF Receiver Front-End for Multi-Band UWB Wireless System
(2007)
Hsiung, Zi-Hao
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Wu, Hui-I
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Jou, Christina F.
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電信工程研究所
;
Institute of Communications Engineering
This paper demonstrates a RF receiver front end circuit for multi-band orthogonal frequency division multiple access (MB-OFDM) using standard 0.18um complementery metal oxide semiconductor (CMOS) technology. The receiver front end includes a low-noise amplifier and a down conversion mixer. The proposed LNA uses transistor's intrinsic capacitor Cgd and only one inductor as input matching network to achieve wideband impedance matching. And the proposed mixer uses folded current reused architecture to decrease supply voltage and enhance conversion power gain effectively. This wideband front end circuit achieves 19-21.5 dB of power gain and 4-3-6.2 dB of double-sideband (DSB) noise figure from 3.1GHz to 8 GHz with IF=100 MHz. The simulated core current consumption was 13.1 mA from a 1.5 V supply, with a compact size of 1.16 mm(2).
A DC-20GHz CMOS Active Power Divider Design
(2010-01-01)
Huang, Jing-Ying
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Wu, Hui-I
;
Hu, Robert
;
Jou, Christina F.
;
Niu, Dow-Chi
We report the design of a wideband active power divider using commercial CMOS process. This circuit is made of two distributed amplifiers sharing a common input artificial transmission line while two distinct transmission lines are employed for the output ports. Since the input transmission line tends to be overly capacitive now when compared with the conventional distributed amplifier, the constituting gain cells need to be revised so as to retain the intended 20GHz bandwidth. Small input and output reflection coefficients have been observed, and the measured output port isolation is below -30dB across the whole bandwidth, which is beyond the reach of passive power dividers. Magnitude and phase imbalances of the two output ports are 0.2dB and 0.4 degrees at 15GHz and 0.9dB and 0.6 degrees at 20GHz. The noise figure is 6.9dB at 15GHz and 9.4dB at 20GHz. The input-referred 1dB compression point is -9.5dBm at 15GHz and -10.5dBm at 20GHz. With the bias of 2.5Volt and 64Amp, the total power dissipation is 160mWatt.
A Folded Current-Reused Down-Converter Mixer for Ultra Wide-Band Applications
(2007)
Hsiung, Zi-Hao
;
Wu, Hui-I
;
Jou, Christina F.
;
電信工程研究所
;
Institute of Communications Engineering
This paper demonstrates an ultra-wideband mixer using TSMC 0.18 um mixed-signal/RF CMOS 1P6M technology. The main idea is to replace the traditional common source trans-conductance stage with a folded current-reused pair. It can enhance conversion power gain effectively without additional power consumption. And the folded approach is used to reduce supply voltage. To achieve wideband frequency response, second-order LC ladder wideband input matching network is utilized. This wide-band mixer achieves measured conversion power gain of 13.5-15.5 dB and a DSB noise figure of 11-14.5 dB from 3.1GHz to 8 GHz. The dc power consumption is 11.25 mW under a supply voltage of 1.5 V, with a compact sin of 0.83 mm(2).
A low phase noise design for ultrawideband frequency synthesizer
(2007-05-01)
Chang, Po-Yang
;
Wu, Hui-I
;
Jou, Christina F.
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傳播研究所
;
Institute of Communication Studies
A low phase-noise frequency synthesizer design for ultrawideband is demonstrated in a 0.18-mu m CMOS process. It combines a low phase-noise voltage-controlled oscillator with two-stage dividers and a switched buffer multiplexer with low layout complexity. Because of the symmetrical independent architecture of this switch buffer design, it can reduce the additional phase noise created by the traditional multiplexer stage. Here, this low phase noise design in three LO bands (8448, 4224, and 2112 MHz) is demonstrated. The measurement shows that in these three LO band, this new structure can achieve phase noise of less than - 121 dBc/Hz at I MHz offset. The frequency tuning range is 10% while consuming only 52.2 mW from a 1.8-V supply. (c) 2007 Wiley Periodicals, Inc.
A New Sub-harmonic Mixer Using Switched Gm Technique For 802.11a/b/g Dual-Band Receivers
(2007)
Chang, Win-Ming
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Wu, Hui-I
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Jou, Christina F.
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電信工程研究所
;
Institute of Communications Engineering
A new prototype of sub-harmonic mixer using switched Gm technique is designed and implemented in a standard 0.18um CMOS technology. By using the PMOS active load and a switched Gm prototype at LO port, the new sub-harmonic mixer can achieve high conversion power gain and still maintain high linearity, and we can alleviate the shortage of the voltage headroom at IF output. In addition, it consumes no DC power while there is no LO input. At 5.2-GHz ISM band, this fully integrated sub-harmonic mixer achieves measured high conversion power gain of 12.8dB, -1.8dBm input third order intercept point (IIP3), and 14.0dB noise figure at 10-MHz with 4dBm LO power.
A Quadrature Voltage Controlled Oscillator with 9 Selective Bands for UWB Communication
(2007)
Chang, Po-Yang
;
Wu, Hui-I
;
Jou, Christina F.
;
電信工程研究所
;
Institute of Communications Engineering
A 9 bands quadrature voltage-controlled oscillator (QVCO) for UWB communciation operating from 2 to 10 GHz is presented. The architecture consists of a wideband quadrature voltage-controlled oscillator (QVCO), 2-stage dividers, switch buffer and only one quadrature single-sideband (SSB) mixer. Fabricated in 0.18-mu m CMOS technology, this work achieves QVCO's measured phase noise less than -98 dBc/Hz at 1 MHz offset, and the simulated output powers of twelve bands have better than 35 dB sideband rejection while consuming 58.7mW of the core circuit and 48.7mW of the buffer from a 1.8-V supply. The simulated switching time for hopping frequency is about 1ns.
Complementary UWB LNA Design Using Asymmetrical Inductive Source Degeneration
(2010-07-01)
Wu, Hui-I
;
Hu, Robert
;
Jou, Christina F.
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電信工程研究所
;
Institute of Communications Engineering
This letter proposes a novel LNA design method where the complementary transistor topology is combined with asymmetrical inductive source degeneration to achieve matched input impedance over a wide bandwidth. A 2-10 GHz LNA is designed and fabricated using a commercial 0.18 mu m RF-CMOS process to verify the feasibility of our proposed method. In the intended bandwidth, this LNA has matched input impedance, 20 dB power gain, and 2.4-3.4 dB noise figure, with 25.65 mW power consumption.
Design of Compact Ultra-Wideband Filter with Low Insertion Loss and Wide Stopband
(2010-09-01)
Wu, Hui-I
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Wong, Zhao-Zhu
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Jou, Christina F.
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電信工程研究所
;
Institute of Communications Engineering
This paper proposes a compact ultra-wideband filter, which skillfully utilizes the magnetic and capacitive coupling to obtain sharp rejection. And, the filter contains a small number of lossy elements, thus the low insertion loss and compact size will not be compromised. The measured results show that the filter prototype has a measured 3 dB fractional bandwidth of 128% from 2.8 GHz to 11.4 GHz, a minimum insertion loss of 0.3 dB within the passband, a superior 20 dB stopband rejection from 12.4 GHz to 24 GHz, and a very compact circuit size of 0.23 lambda x 0.31 lambda, where lambda is the guided wavelength of the microstrip structure at the center frequency f(0) = 7.1 GHz.
Novel wideband CMOS LNA with only an inductor as input matching network
(2007)
Hsiung, Zi Hao
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Wu, Hui-I
;
Jou, Christina. F.
;
傳播研究所
;
Institute of Communication Studies
A 3-8GRz wide-band low noise amplifier with novel input matching mechanism is presented in this letter. The proposed circuit uses transistor's intrinsic capacitor Cgd and only one inductor as input matching network to achieve a measured -10 dB input reflection coefficient from 2.75 GM to 12 GM. The fabricated wideband LNA achieves a measured average power gain (S21) of about 10 dB and noise figure of 3.64-5.5dB from 2.75 to 7.5 GHz.
Wideband Matched CMOS LNA Design Using R-L-C Loading Network
(2010-09-01)
Wu, Hui-I
;
Horng, Qi-Yuan
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Hu, Robert
;
Jou, Christina F.
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電子工程學系及電子研究所
This paper proposes a new methodology for designing and analyzing wideband matched CMOS LNA with R-L-C loading network, where validity of this new approach is supported by the agreement between the simulated input impedance of the LNA and its calculated counterpart. To demonstrate its feasibility, two wideband matched LNA's are designed using TSMC 0.18-mu m RF-CMOS process. One is for 3-8 GHz application and the second one targets at 8-25 GHz frequency range. The measured results of both circuits will then be presented.