Browsing by Author "Wu, JC"

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A 0.99 mu A operating current Li-ion battery protection IC
(2002-05-01)
Shyu, YS
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Wu, JC
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A lithium-ion (Li-ion) battery protection IC with an average current of 0.99 muA (at a battery voltage of 3.6 V) and a standby current (after detecting over-discharge) less than 0.01 muA is presented. This low power performance is achieved via a power-on duty-cycle technique. The protection circuit samples the voltage of the battery periodically and powers down during the rest of time. This Li-ion battery protector provides overcharge, over-discharge, excess-current and short circuits protection. This protection IC was implemented in a 0.6-mum CMOS technology and the active area is 880 mum x 780 mum.
A 256 mA 0.72 V ground bounce output driver
(2000-05-01)
Yu, PC
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Chang, HH
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Wu, JC
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A new output driver design called modified asymmetrical slew rate (MASR) output driver was proposed to reduce the simultaneous switching noise without sacrificing switching speed, for high speed and heavy loading applications. The driving capability of the output driver was designed to sink/source 64mA current @ V-OL/V-OH = 0.4V/4.6V, with 66pF and 50 Omega loading. When four drivers switch simultaneously, the ground bounce was design to be less than 0.8 V. The performances of the conventional, controlled slew rate (CSR), and MASR output drivers were analyzed by computer simulation. These three types of drivers were implemented with a 0.8 mu m CMOS process. The measured ground bounce of the conventional driver is 1.22 V, while the ground bounce of the MASR driver is reduced to 0.72 V. The propagation delays of the conventional and MASR drivers are the same. The performance of the MASR driver is better than that of the CSR driver in all aspects.
A 30 V high voltage NMOS structure design in standard 5 VCMOS processes
(2003-11-01)
Lin, TC
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Wu, JC
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper describes the robust design of the 30 V high voltage NMOS (HVNMOS) structure implemented in a 0.6 mum 5 V standard CMOS processes without any additional masks or process steps. The structure makes use of the field oxide (FOX) and light doping N-well to increase the drain to gate and drain to bulk breakdown voltages, respectively. By varying the six spacing parameters: the channel length, gate overlap FOX, N-well overlap channel length, poly to the active area of the drain (OD2), metal extend beyond the OD2 and N-well extend beyond the OD2 in HVNMOS structure. the breakdown voltage can be improved. The experimental results show that the breakdown voltage of the normal NMOS is 11V, and the breakdown voltage of the HVNMOS is increased to over 30 V. With the optimized layout parameters of the HVNMOS, it can be increased to 38 V.
A 60 mu A quiscent current, 250 mA CMOS low dropout regulator
(2001-05-01)
Shyu, YS
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Wu, JC
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A fully integrated Low Dropout (LDO), low quiescent current regulator has been fabricated in a 0.6 mum CMOS technology. It is stable with low and high effective series resistance (ESR) capacitors. A dynamic feedback (DNFB) bias technique is used to bias the error amplifier in the LDO such that good current efficiency is achieved while maintaining a good transient response. In order to compare the performance of the LDO regulators with and without dynamic feedback, the error amplifiers are configured to have a large bias current (LC), a small bias current (SC) and a bias with dynamic feedback current using switches. The measurement results show that DNFB's line and load regulations are 0.145%/V and 11 ppm/mA, respectively. Besides, there is about 33% reduction in settling time and voltage drop compared with SC LDO when load current is switching from 0 mA to 50 mA. In order to reduce the dropout voltage, a dropout reduction circuitry based on DNFB is also designed to reduce the threshold voltage of LDO's output PMOS. The measured dropout reduction is 8.1 mV which carl be further reduced by a larger feedback ratio in DNFB. The quiescent current of this LDO is measured to be 59.4 muA and this LDO can provide a maximum output current of 250 mA. at an input voltage of 3.6 V. The active area of this LDO is 760 mum x 714 mum.
A 723-MHz 17.2-mW CMOS programmable counter
(1998-10-01)
Chang, HH
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Wu, JC
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A high-speed complementary metal-oxide-semiconductor (CMOS) programmable divide-by-N frequency divider was proposed, Using a new end-of-count (EOC) detecting and reloading algorithm, the reloading delay is distributed over three clock cycles, which increases the operating frequency. The simulated operating frequency of the new counter is 581 MHz, which is 2.2 times higher than that of a conventional programmable counter. The new programmable counter was implemented in a 0.8-mu m CMOS technology. The active die area is 480 x 100 mu m. The counter was measured to operate at 723 MHz with 5 V power supply and dissipates 17.12 mW.
A 723-MHz 17.2-mW CMOS programmable counter
(1998-10-01)
Chang, HH
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Wu, JC
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A high-speed complementary metal-oxide-semiconductor (CMOS) programmable divide-by-N frequency divider was proposed, Using a new end-of-count (EOC) detecting and reloading algorithm, the reloading delay is distributed over three clock cycles, which increases the operating frequency. The simulated operating frequency of the new counter is 581 MHz, which is 2.2 times higher than that of a conventional programmable counter. The new programmable counter was implemented in a 0.8-mu m CMOS technology. The active die area is 480 x 100 mu m. The counter was measured to operate at 723 MHz with 5 V power supply and dissipates 17.12 mW.
A class-B output buffer for flat-panel-display column driver
(1999-01-01)
Yu, PC
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Wu, JC
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Due to the large number of output buffers on a column driver chip of a hat-panel display, the quiescent current and die area of the output buffer must be minimized. This paper presents a low static power, Large output swing, and wide operating voltage range class-B output buffer amplifier for driving the large column Line capacitance in flat-panel display. rt comparator is used in the negative feedback path to eliminate quiescent current in the output stage. The proposed output buffer circuit was implemented in a 0.8-mu m CMOS process. Its output voltage suing is from 1 V to the supply voltage, With 5-V supply and 600-pF toad, the maximum tracking error is +/-7 mV. The measured static current is 24 mu A. The settling time for 4-V suing to within 0.2% is 8 mu s, which is more than adequate for driving 1280 x 1024 pixels Liquid crystal displays with 86-Hz frame rate and 256 gray levels in each color.
A compact low-power rail-to-rail class-B buffer for LCD column driver
(2002-08-01)
Weng, MC
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Wu, JC
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper proposes a compact, low-power, and rail-to-rail class-B output buffer for driving the large column line capacitance of LCDs. The comparator used as a nonlinear element in feedback path is modified from the current-mirror amplifier, which has area and power advantages. The output buffer was realized in a 0.35 mum CMOS process. The active area of the buffer is 86 X 73.5 mum(2). With a 3.3 V supply, the measured quiescent current is 7.4 muA. The settling time for 0.05-3.25 V swing to within 0.2% is 8 mus.
A light-induced tunneling state in a submicron double barrier tunneling diode with a center-doped well
(2000-02-01)
Suen, YW
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Young, CC
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Chang, CJ
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Wu, JC
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Wang, SY
We will present the observation of a light-induced meta-stable impurity state in a submicron center-doped double barrier tunneling diode (DBRTD) manufactured by a novel single-step e-beam lithography process in which no further alignment for the interconnect between the bonding pad and the small active device region is required. We attribute the mete-stable tunneling state, which can be switched by light and high voltage bias, to the light- or field-induced charge redistribution in the active tunneling region. (C) 2000 Elsevier Science B.V. All rights reserved.
A novel driving scheme for FLCD
(1996)
Wu, JC
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Wang, CC
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A reverse-voltage protection circuit for MOSFET power switches
(2001-01-01)
Hong, HP
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Wu, JC
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
When MOSFET is used as a power switch, if is essential to prevent reverse current flow through the parasitic body diodes under reverse voltage condition. A new built-in reverse voltage protection circuit for MOSFETs has been developed. In this design, an area-efficient circuit is used to automatically select the proper well bias voltage to prevent reverse current under the reverse-voltage condition. This built-in reverse protection circuit has been successfully implemented in a high-side power switch application using a 0.6-mum CMOS process. The die area of the protection circuit is only 2.63 % of that of a MOSFET. The latch-up immunity is greater than +12 V and -10 V in voltage triggering mode, and greater than +/-500 mA in current triggering mode, The protection circuit is not in series with the MOSFET switch, so that the full output swing and high power efficiency are achieved.
A sliding-mode approach to fuzzy control design
(1996-03-01)
Wu, JC
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Liu, TS
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交大名義發表
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機械工程學系
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National Chiao Tung University
This study develops a method for fuzzy control design with sliding modes in which robustness is inherent, Fuzzy control is formulated to become a class of variable structure system (VSS) control, Sliding modes are used to determine best values for parameters in fuzzy control rules, thereby robustness in fuzzy control can be improved. A switching manifold is prescribed and the phase trajectory is demanded to satisfy both the reaching condition and the sliding condition for sliding modes, Both computer simulations and experiments are carried out for an apparatus which can to some extent represent cornering motion of a motorcycle on which a rider leans to maintain stability, Experimental results demonstrate that the proposed method outperforms both proportional integral derivative (PID) control and neural-network-based fuzzy control.
A spread spectrum clock generator for EMI reduction
(2001-12-01)
Chen, HW
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Wu, JC
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper described a new method to generate a spread spectrum clock for the purpose of EMI reduction. This method uses two phase-locked loops (PLL). The output of the first PLL is locked to its input of 14.318-MHz, The VCO in this PLL is used to produce 32 outputs with the same frequency and each with 11.25 degrees phase variation. A digital spread spectrum generator uses these 32 signals to generate the desired spread spectrum signal by phase hopping technique. These two circuits form a spread spect ruin digital PLL (SSDPLL). The second PLL is configured as a conventional frequency synthesizer. It can be programmed to generate the desired frequencies. The second PLL also serves as a low pass filter of the output of the SSDPLL to smooth out frequency variation. This circuit was implemented with a 0.6 mum single poly CMOS process. The active areas of the SSDPLL and the synthesizer are 826 x 396 mum(2) and 790 x 298 mum(2), respectively. The, total power consumption is 99 mW at 3.3 V supply. The peak power of the spread spectrum clock is reduced by 10 dBm at 14.318 MHz output with a 2.34% frequency spreading. The reduction of peak power increases with output frequency.
A two-step A/D converter in digital CMOS processes
(2002)
Lin, TC
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Wu, JC
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper describes a 3V 8-bit 50MSPS two-step analog-to-digital converter implemented in a 0.35mum 1P4M logic CMOS process. A PMOS biased in accumulation mode was used as a coupling capacitor in this ADC, so that the more expensive mixed mode process with double poly or MIM capacitors can be avoided. A modified switch box which greatly reduces the number of switches needed was also presented in this paper. The modified switch box can reduce the capacitance loading effect, of the resistor ladder DAC (R-DAC) and thus making the settling time of the DAC faster. The ADC occupies a die area of 0.38mm(2) (450mum*850mum) and dissipates 64mW at 50MHz clock rate with 3V single supply voltage. The FFT simulation result shows that the SNDR is 48.18dB at 5MHz input frequency and 50MSPS conversion rate and the static simulation shows that the max. INL/DNL is less than 0.5LSB/0.5LSB.
An integrated digital PWM DC/DC converter
(2000)
Tso, CH
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Wu, JC
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, a simple, integrated, and digitally controlled PWM DC/DC converter is proposed. All circuits can be implemented on a single chip. Behavior modeling and techniques for increasing resolution for this digital controller are also discussed. Despite of its simple architecture, simulation results show competitive performance among general PWM converters.
Analysis and implementation of proportional current feedback technique for digital PWM DC-DC converters
(2003-11-01)
Tso, CH
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Wu, JC
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, a novel technique using proportional current feedback is proposed to improve dynamic response of digital PWM DC-DC converters. Generally, digital controllers are implemented using microprocessors or DSPs. Additional A/D converters are required to sense feedback signals. Proposed simple structure makes it feasible to integrate both A/D converter and digital controller on a single chip. System complexity and hardware cost are therefore greatly reduced. A behavioral time domain circuit model is proposed and analyzed using MATLAB. Both simulation and experimental results showed satisfactory performance to meet power requirements of microprocessors.
Anisotropic pinning effect on a Nb thin film with triangular arrays of pinning sites
(2004-06-01)
Wu, TC
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Kang, PC
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Horng, L
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Wu, JC
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Yang, TJ
A superconducting Nb thin film with triangular arrays of pinning sites has been fabricated to investigate the commensurate vortex lattices. Vortex-vortex interactions in this pattern film make the observed anisotropy in the pinning properties. Periodic minima appear in the magnetoresistance curves at equal field intervals that can be associated with matching effect. The transport properties at near critical temperatures show anisotropic pinning properties related to the configuration of pinning centers. The critical current is depressed when the driving force is applied along the short diagonal in the rhombic unit cell of pinning array. It implies that the pinning potential along the short diagonal creates a moving channel of vortices in triangular arrays of defects. The pinned and interstitial vortices can be movable in an incommensurate vortex row and a straight unhindered one-dimensional path. (C) 2004 American Institute of Physics.
Bilingual sentence alignment based on punctuation statistics and lexicon
(2005)
Chuang, TC
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Wu, JC
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Lin, T
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Shei, WC
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Chang, JS
This paper presents a new method of aligning bilingual parallel texts based on punctuation statistics and lexical information, It is demonstrated that the punctuation statistics prove to be effective means to achieve good results. The task of sentence alignment of bilingual texts written in disparate language pairs like English and Chinese is reportedly more difficult. We examine the feasibility of using punctuations for high accuracy sentence alignment. Encouraging precision rate is demonstrated in aligning sentences in bilingual parallel corpora based solely on punctuation statistics. Improved results were obtained when both punctuation statistics and lexical information were employed. We have experimented with an implementation of the proposed method on the parallel corpora of Sinorama Magazine and Records of the Hong Kong Legislative Council with satisfactory results.
Data line driver design for a 10'' 480x640x3 color FED
(1996)
Wang, CC
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Wu, JC
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Huang, CM
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交大名義發表
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電子工程學系及電子研究所
A data line driver with 120 outputs and capable of producing contrast ratio over 100 for a 10'' 480x(640x3) pixels color field emission display (FED) panel have been designed. Three phase clocks were used to reduce the maximum operating frequency to 22.68Mhz. A class AB Op Amp was used as the analog output buffer to reduce the power dissipation. The chip is implemented in a 24V CMOS process, chip size is 7620 mu m x 17500 mu m.
Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology
(1999-02-01)
Chang, HH
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Ker, MD
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Wu, JC
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A novel dynamic-floating-gate technique is proposed to improve ESD robustness of the CMOS output buffers with small driving/sinking currents. This dynamic-floating-gate design can effectively solve the ESD protection issue which is due to the different circuit connections on the output devices. By adding suitable time delay to dynamically float the gates of the output NMOS/PMOS devices which are originally unused in the output buffer, the human-body-model (machine-model) ESD failure threshold of a 2-mA output buffer can be practically improved from the original 1.0 kV (100 V) up to greater than 8 kV (1500 V) in a 0.35-mu m bulk CMOS process. (C) 1998 Elsevier Science Ltd. All rights reserved.