Browsing by Author "Wu, JT"

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1.2V CMOS switched-capacitor circuits
(1996)
Wu, JT
;
Chang, YH
;
Chang, KL
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 125 MHz 86 dB IM3 programmable-gain amplifier
(2002)
Hsu, CC
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A digitally programmable-gain amplifier (PGA) is realized using a 0.35 mum CMOS technology. Constant bandwidth and high linearity are achieved by using a current-mode amplifier with resistor-network feedback. The PGA has a voltage gain varying from 0 dB to 19 dB with a bandwidth of 125 MHz. With 1 Vpp output, the third-order intermodulation (IM3) of the PGA is -86 dB at 10 MHz and -59 dB at 80 MHz. The distortion is also insensitive to the gain change. The circuit dissipates 21 mW from a 3.3 V supply.
A 125MHz 8b digital-to-phase converter
(2003)
Chou, JM
;
Hsieh, YT
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration
(2005-05-01)
Liu, HC
;
Lee, ZM
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This study presents a 15-b 40-MS/s switched-capacitor CMOS pipelined analog-to-digital converter (ADC). High resolution is achieved by using a correlation-based background calibration technique that can continuously monitor the transfer characteristics of the critical pipeline stages and correct the digital output codes accordingly. The calibration can correct errors associated with capacitor mismatches and finite opamp gains. The ADC was fabricated using a 0.25-mu m 1P5M CMOS technology. Operating at a 40-MS/s sampling rate, the ADC attains a maximum signal-to-noise-plus-distortion ratio of 73.5 dB and a maximum spurious-free-dynamic-range of 93.3 dB. The chip occupies an area of 3.8 x 3.6 mm(2), and the power consumption is 370 mW with a single 2.5-V supply.
A 15-bit 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration (vol 40, pg 1047, 2005)
(2005-11-01)
Liu, HC
;
Lee, ZM
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 15b 20MS/s CMOS pipelined ADC with digital background calibration
(2004)
Liu, HC
;
Lee, ZM
;
Wu, JT
;
交大名義發表
;
National Chiao Tung University
A 2-V 2-GHz BJT variable frequency oscillator
(1998-09-01)
Chen, WZ
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new LC-tuned negative-resistance variable-frequency oscillator (VFO) is described. Frequency tuning is accomplished by using a variable-impedance converter (VIC) to simulate the varactor function, A negative-impedance converter provides the necessary negative resistance for oscillation and also functions as the voltage level shifters for the VIC. A low-voltage translinear circuit is used to linearize the tuning characteristic of the VFO. Implemented in a 0.8 mu m 12 GHz f(T) BiCMOS technology, the VFO has a tuning range from 1.55 to 2.02 GHz, while consuming 15 mA from a -2 V supply.
A 2-V, 1.8-GHz BJT phase-locked loop
(1999-06-01)
Chen, WZ
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper describes the design of a bipolar junction transistor phase-locked loop (PLL) for Sigma Delta fractional-N frequency-synthesis applications. Implemented in a 0.8-mu m BICMOS technology, the PLL can operate up to 1.8 GHz while consuming 225 mW of power from a single -2-V supply. The entire LC-tuned negative-resistance variable-frequency oscillator is integrated on the same chip. A differential low-voltage current-mode logic circuit configuration is used in most of the PLL's functional blocks to minimize phase jitter and achieve low-voltage operation. The multimodulus frequency divider is designed to support multibit digital modulation. The new phase and frequency detector and loop filter contain only npn transistors and resistors and thus achieve excellent resolution in phase comparison. When phase locked to a 53.4-MHz reference clock, the measured phase noise of the 1.6-GHz output is -91 dBc/Hz at 10-kHz offset, The frequency switching time from 1.677 to 1.797 GHz is 150 mu s. Die size is 4300 x 4000 mu m(2), including the passive loop filter.
A 2V 100MHz CMOS vector modulator
(1997)
Wu, JT
;
Chang, HD
;
Chen, PF
;
交大名義發表
;
電子工程學系及電子研究所
A 2V 2GHz BJT variable-frequency oscillator
(1997)
Chen, WZ
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An LC-tuned negative-resistance variable-frequency oscillator (VFO) is described. Frequency tuning is accomplished by using a variable impedance converter to simulate the varactor function. Implemented in a 0.8 mu m 12 GHz f(T) BiCMOS technology, the VFO has a tuning range from 1.55 GHz to 2.02 GHz, while consuming 15 mA from a -2 V supply.
A 33-mW 12-bit 100-MHz sample-and-hold amplifier
(2002)
Hsu, CC
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of pre-charging and output capacitor coupling can mitigate the requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 mum CMOS technology, the SHA achieves 73 dB SFDR for 2 Vpp input at 100 MHz sampling rate. The performance is not degraded for input's frequency up to the Nyquist frequency. Power consumption is 33 mW from a single 2.5 V supply.
A background comparator calibration technique for flash analog-to-digital converters
(2005-01-01)
Huang, CC
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A background comparator calibration technique for flash analog-to-digital converters
(2005-09-01)
Huang, CC
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a background calibration technique for trimming the input-referred offsets of the comparators in a flash analog-to-digital converter (ADC) without interrupting the ADC's normal operation. For a random-chopping comparator, the polarity of its offset is detected by observing the code density of its comparison results. Binary feedback is then used to digitally adjust the comparator's offset so that the offset is minimized. All calibration procedures are performed in the digital domain. The calibration performance is characterized by the converging speed of the feedback loop and the offset fluctuation due to the disturbance of the ADC's input. These two performance indexes of a background-calibrated comparator (BCC) are determined by three parameters: the probabilistic distribution of the ADC's input, the BCC's offset quantized step size, and the threshold of an internal bilateral peak detector. The offset fluctuation of a BCC can be drastically reduced by employing a windowing mechanism. The use of windowed BCCs in a flash ADC can introduce nonmonotonic-threshold (NMT) effects which include an increase in calibration settling time and an increase in sigma(V-OS). The use of uncorrelated random chopping for neighboring BCCs can ensure the validity of offset detection and mitigate the NMT effects.
A background timing-skew calibration technique for time-interleaved analog-to-digital converters
(2006-04-01)
Wang, CY
;
Wu, JT
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a background timing-skew calibration technique for time-interleaved analog-to-digital converters (ADCs). The timing skew between any two adjacent analog-digital (AID) channels is detected by counting the number of zero crossings of the ADCs input while randomly alternating their sampling sequence. Digitally controlled delay units are adjusted to minimize the timing skews among the AID channels caused by the mismatches among the clock routes. The calibration behaviors, including converging speed and timing jitter, are theoretically analyzed and verified with simulations. A 6-bit 16-channel ADC is used as an example.
A CMOS 33-mW 100-MHz 80-dB SFDR sample-and-hold amplifier
(2003-10-01)
Hsu, CC
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 mum CMOS technology, the SHA achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp output at 100MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm(2) and dissipates 33mW from a single 2.5V supply.
A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier
(2003-10-01)
Hsu, CC
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A highly linear programmable-gain amplifier (PGA) is fabricated using a 0.35-mum CMOS technology. High linearity and constant wide bandwidth are achieved by using a high-gain amplifier with low input impedance and resistor-network feedback. The voltage gain is varied by digitally controlling the input switched resistors. The distortion of a switched resistor has been analyzed using the Volterra series. The PGA has a voltage gain varying from 0 to 19 dB, while maintaining a constant bandwidth of 125 MHz. The third-order intermodulation distortion is -86 dB at 10 MHz. The circuit dissipates 21 mW from a 3.3-V supply.
A robust background calibration technique for switched-capacitor pipelined ADCs
(2005)
Fan, JL
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work presents a robust background calibration scheme for switched-capacitor (SC) pipelined analog-to-digital converters. A SC multiplying digital-to-analog converter (MDAC) is usually linearized by high-gain capacitive feedback. Its conversion gain can be measured by splitting the input sampling capacitor and injecting a random sequence into the signal path. The magnitude of the random sequence can be extracted later in the digital domain. The use of input-dependent generation of the random sequence can eliminate the extra signal range requirement and also save calibration time. Furthermore, the use of random choppers to scramble signal can ensure that all necessary calibration data can be collected within a given time regardless of input conditions, resulting in a more robust ADC.
A statistical background calibration technique for flash analog-to-digital converters
(2004)
Huang, CC
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new background calibration technique is described to digitally trim the input-referred offset voltage of comparators in a high-speed flash analog-to-digital converters. The polarity of comparator's offset is detected by observing the output code density of a random chopping comparator. Binary feedback is used to adjust the comparator's offset. All calibration processing is performed in the digital domain. thus minimizing the overhead for analog circuitry. Two key design parameters are the comparator's trimming step and the thresholds of a peak detector, which determine the offset's standard deviation and the time constant of the calibration loop.
Digital background calibration technique for pipelined analog-to-digital converters
(2003)
Liu, HC
;
Lee, ZM
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new background calibration technique for pipelined analog-to-digital converters is proposed. By dividing the step sizes of the multiplying digital-to-analog converter (MDAC) in a pipeline stages and injecting a random signal into the MDAC, it is possible to calibrate a pipeline stage without interrupting the normal analog-to-digital operation. The calibration can eliminate the nonlinear effects due to the MDAC's gain error, input offset voltage, and output errors in the digital-to-analog conversion.
Low supply voltage CMOS charge pumps
(1997)
Wu, JT
;
Chang, KL
;
交大名義發表
;
電子工程學系及電子研究所
;
National Chiao Tung University
Charge pumps that can operate under a low supply voltage are described. The use of charge transfer switches (CTSs) can improve the voltage pumping gain, applying dynamic control to the CTSs can reduce reverse currents. Appending bootrapped output stages to the new charge pumps can further expand the maximum output voltage.