A 33-mW 12-bit 100-MHz sample-and-hold amplifier

Abstract

A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of pre-charging and output capacitor coupling can mitigate the requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 mum CMOS technology, the SHA achieves 73 dB SFDR for 2 Vpp input at 100 MHz sampling rate. The performance is not degraded for input's frequency up to the Nyquist frequency. Power consumption is 33 mW from a single 2.5 V supply.