Browsing by Author "Wu, MS"

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A new path delay test scheme based on path delay inertia
(2004)
Chen, CL
;
Lee, CL
;
Wu, MS
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper proposes a new path delay test scheme based on path delay inertia. The scheme only applies pulses of specified widths, which are proportional to path delays, to paths-under-test. It is simple, eliminating the conventional two-pattern test for delay faults. Issues, such as sensitivity of applied pulse widths w.r.t. path delay, related with the scheme were studied and an experimental chip was implemented to demonstrate the scheme.
A testing scheme for crosstalk faults based on the oscillation test signal
(2002)
Wu, MS
;
Lee, CL
;
Chang, CP
;
Chen, JE
;
電子工程學系及電子研究所
A test scheme for the crosstalk fault based on the oscillation signal is proposed. It uses an oscillation signal applied on an affecting line and detects induced pulses on a victim line if a crosstalk fault exists between these two lines. It is simple and eliminates the complicated timing issue during test generation for the crosstalk fault in the conventional approaches. The test generation and fault simulation based on the scheme are described. Experimental results are also presented to show the described test generation procedure is effective in generating test patterns for this scheme.
Crosstalk fault detection for interconnection lines based on path delay inertia principle
(2005)
Wu, MS
;
Lee, CL
;
Chang, YJ
;
Wu, WC
;
電子工程學系及電子研究所
The crosstalk fault becomes more and more important in the deep submicron SoC and its detection involves sophisticated timing measurement. In this paper a new test scheme to detect the crosstalk fault, based on the path delay inertia, for interconnection lines in SoC is proposed. The scheme, without using timing measurement, applies a transition on the aggressor line and a critical width pulse, CWP to the victim line and detects the propagation of the CWP at the output of the victim line. The scheme is simple and simulation analysis and experiments show that it is effective in detecting crosstalk faults.
Oscillation ring delay test for high performance microprocessors
(2000)
Wu, WC
;
Lee, CL
;
Wu, MS
;
Chen, JE
;
Abadir, MS
This paper proposes a new test scheme, oscillation ring test, and its associated test circuit organization for delay fault testing for high performance microprocessors. For this test scheme, the outputs of the circuit under test are connected to its inputs to form oscillation rings and test vectors which sensitize circuit paths are sought to make the rings oscillate. High speed transition counters or oscillation detectors can then be used to detect whether the circuit is working normally or not. The sensitizable paths of oscillation rings cover all circuit lines, detecting all gate delay faults, a large part of hazard free robust path delay faults and all the stuck-at faults. It has the advantage of testing the circuit at the working speed of the circuit. Also, with some modification, the scheme can also be used to measure the maximum speed of the circuit. The scheme needs minimal simple added hardware, thus ideal for testing, embedded circuits and microprocessors.
Using a periodic square wave test-signal to detect crosstalk faults
(2005-03-01)
Wu, MS
;
Lee, CL
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This BIST scheme simplifies the detection of crosstalk faults in deep-submicron VLSI circuits in the boundary scan environment. Simulation results show that with just a few random patterns fault coverage for. most large benchmark circuits can exceed 90%.