Browsing by Author "Wu, Meng-Chen"

Now showing 1 - 5 of 5

Design-for-Debug Layout Adjustment for FIB Probing and Circuit Editing
(2011)
Chen, Kuo-An
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Chang, Tsung-Wei
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Wu, Meng-Chen
;
Chao, Mango C. -T.
;
Jou, Jing-Yang
While the technology node continually and aggressively scales, the resolution of FIB techniques does not scale as fast. Thus, the percentage of nets which can be observed or repaired through FIB probing or circuit editing is significantly decreased for advanced process technologies, which limits the candidates that can be physically examined through the FIB techniques during the debugging process. This paper introduces a design-for-debug framework which can adjust the layout to increase the FIB observable rate and the FIB repairable rate for its signals. The layout adjustment is made through pre-defined simple operations subject to the design rules and the timing constraints. Hence, the proposed framework does not require a complicated router as its core and can be applied in conjunction with any commercial APR tool. The experimental result based on an 90nm technology has demonstrated that the proposed DFD framework can effectively increase the FIB observable and repairable rates under different parameter settings while the overall area and circuit performance remain the same.
Mixed Non-Rectangular Block Packing for Non-Manhattan Layout Architectures
(2011)
Wu, Meng-Chen
;
Chen, Hung-Ming
;
Jou, Jing-Yang
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Non-Manhattan structures, such as the X and Y architectures, propose different flavors in reducing the use of physical resources, such as total wirelength and number of vias. However, in order to take full advantage of these structures, we need to develop new tools for these architectures, especially for early stages in physical design. In this paper, we propose the packing algorithm with isosceles right triangular and trapezoidal blocks using the B*-tree representation. Our approach can be further applied to packing with any block which can be divided into rectangles and isosceles right triangles. Experimental results based on the modified MCNC benchmarks show that the average area usage is above 95% and the run time of our proposed algorithm is comparable when performing rectangular and non-rectangular block packing with original B*-tree.
Multiple-Fault Diagnosis Using Faulty-Region Identification
(2009)
Tasi, Meng-Jai
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Chao, Mango C. -T.
;
Jou, Jing-Yang
;
Wu, Meng-Chen
;
電子工程學系及電子研究所
The fault diagnosis has become an increasing portion of today's IC-design cycle and significantly determines product's time-to-market. However, the failure behaviors from the defective chips may not be fully represented by the single fault model. In this paper, we propose a fault-diagnosis framework targeting multiple stuck-at faults. This framework first reports a minimal suspect region, in which all real faults are topologically covered. Next, a proposed ranking method is applied to sieve out the real faults from the candidates within the suspect region. The experimental results show that the proposed diagnosis framework can effectively locate the multiple stuck-at faults within a neighborhood, which may generate erroneous signals cancelling one another and are difficult to be diagnosed based on a single-fault-model method.
Performance constraints aware voltage islands generation in SoC floorplan design
(2006)
Lu, Ming-Ching
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Wu, Meng-Chen
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Chen, Hung-Ming
;
Jiang, Hui-Ru
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電子工程學系及電子研究所
Using voltage island methodology to reduce power consumption for System-on-a-Chip SoQ designs has ecome more and more popular rec. Currently this approach has been considered either in system-level architecture or post-placement stage. Since hierarchical design and reusable intellectual property (IEP) are widely used, it is necessary to optimize floorplanning/placement methodolo considering voltage islands generation to solve power anFcritical path delay problems. In this paper, we propose a floorplanning methodology considering voltage islands generation and performance constraints. Our method is flexible and can be extended to hierarchical design. The experimental results on some MCNC benchmarks show that our method is effective in meeting performance constraints and simultaneously considers the tradeoff between power routing cost and the assignment of supply voltage in mosules.
Performance-Constrained Voltage Assignment in Multiple Supply Voltage SoC Floorplanning
(2009-12-01)
Wu, Meng-Chen
;
Lu, Ming-Ching
;
Chen, Hung-Ming
;
Jou, Jing-Yang
;
電子工程學系及電子研究所
Using voltage island methodology to reduce power consumption for System-on-a-Chip (SoC) designs has become more and more popular recently. Currently this approach has been considered either in system-level architecture or postplacement stage. Since hierarchical design and reusable intellectual property (IP) are widely used, it is necessary to optimize floorplanning/placement methodology considering voltage islands generation to solve power and critical path delay problems. In this article, we propose a floorplanning methodology considering voltage islands generation and performance constraints. Our method is flexible and can be extended to hierarchical design. The experimental results on some MCNC benchmarks show that our method is effective in meeting performance constraints and can simultaneously consider the tradeoff between power routing cost and total power dissipation.