Browsing by Author "Wu, Ming-Hung"

Now showing 1 - 9 of 9

A Comprehensive Modeling Framework for Ferroelectric Tunnel Junctions
(2019-01-01)
Huang, Hsin-Hui
;
Wu, Tzu-Yun
;
Chu, Yueh-Hua
;
Wu, Ming-Hung
;
Hsu, Chien-Hua
A modeling framework for ferroelectric tunnel junctions (FTJs) that considers nonpolar interfacial layers (ILs), multi-domain polarization, and complete ferroelectric/capacitive/tunneling currents simultaneously is proposed. This model explains both read and write operations including the controversial switching polarities of FTJ. We also provide useful guidelines for optimizing FTJ performance where the location of IL and the effective thickness ratio between ferroelectric and interfacial layers are found to be most critical.
Extremely Compact Integrate-and-Fire STT-MRAM Neuron: A Pathway toward All-Spin Artificial Deep Neural Network
(2019-01-01)
Wu, Ming-Hung
;
Hong, Ming-Chun
;
Chang, Chih-Cheng
;
Sahu, Paritosh
;
Wei, Jeng-Hua
This work reports the complete framework from device to architecture for deep learning acceleration in an all-spin artificial neural network (ANN) built by highly manufacturable STT-MRAM technology. The most compact analog integrate-and-fire neuron reported to date is developed based on the back-hopping oscillation in magnetic tunnel junctions. This novel device is unique because it performs numerous essential neural functions simultaneously, including current integration, voltage spike generation, state reset, and 4-bit precision. The device itself is also a stochastic binary synapse, and thus eases the implementation of the compact all-spin ANN with high accuracy for online training.
Film Profile Engineering (FPE): A New Concept for Manufacturing of Short-Channel Metal Oxide TFTs
(2013-01-01)
Lyu, Rong-Jhe
;
Lin, Horng-Chih
;
Wu, Ming-Hung
;
Shie, Bo-Shiuan
;
Hung, Hsiang-Ting
A film profile engineering (FPE) concept which utilizes the unique features of various deposition tools to tailor and optimize the profile of the deposited films was demonstrated with the fabricated ZnO TFTs. By implementing the PR trimming technique, high performance devices with L < 100 nm can be readily achieved.
Film-Profile-Engineered IGZO Thin-Film Transistors with Gate/Drain Offset for High Voltage Operation
(2016)
Wu, Ming-Hung
;
Lin, Horng-Chih
;
Li, Pei-Wen
;
Huang, Tiao-Yuan
;
電機學院
IGZO transistors with various gate/drain-offset lengths (L-GDO) were fabricated with the film-profile-engineering method. Breakdown voltage (V-BD) of the fabricated devices increases while transconductance (gm) decreases with increasing LGDO. In contrast, threshold voltage and subthreshold swing remain relatively unchanged. VBD of similar to 80 V is obtained with LGDO of 0.3 mu m . Output characteristics with operation voltage up to 50 V are also demonstrated, evidencing the capability of the device for high-voltage operation. Impact of hot-carrier stress is also investigated in this work.
Film-profile-engineered ZnO thin-film transistor with gate/drain offset for high-voltage operation
(2019-06-01)
Wu, Ming-Hung
;
Lin, Horng-Chih
;
Li, Pei-Wen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We report the design and fabrication of ZnO thin-film transistors (TFTs) configured with designed gate-to-drain (G/D)-offset structures and an auxiliary gate (AG) in a film-profile engineering (FPE) approach for back-end-of-line high-voltage (HV) operation. The breakdown voltage (V-BD) of fabricated FPE TFTs is significantly enhanced from 23 to 90 V by changing the G/D-offset length from -0.3 to 0.5 mu m, whereas there is a corresponding decrease in the on-state current and transconductance (G(m)). To boost the on-state current, an AG biased in the range of 0-5 V is designed to effectively modulate the resistivity of the G/D-offset region and improve G(m) by a factor of 2 while keeping V-BD of 65-70 V nearly unchanged. Output characteristics with drain voltage as high as 60 V have been demonstrated, evidencing the promising potential of the ZnO TFTs for HV device applications. (C) 2019 The Japan Society of Applied Physics
Novel InGaZnO inverters utilizing film profile engineering
(2015-08-01)
Lin, Horng-Chih
;
Wu, Ming-Hung
;
Chan, Chin-Wen
;
Lyu, Rong-Jhe
;
Huang, Tiao-Yuan
In this study we cleverly employ the film profile engineering (FPE) concept to fabricate amorphous InGaZnO (a-IGZO) thin-film transistor (TFT)-based inverters with a resistor-or transistor-load. In the fabrication the profiles of major thin films in both load and drive devices can be properly tailored with designed channel dimensions and deposition conditions. Although the inverter with a resistor-load is simpler in structure and fabrication, the switching performance is found to be restricted by the passive load component. The performance can be greatly promoted as a depletion-mode transistor-load is used instead. Full-swing operation is demonstrated for the inverter with a voltage gain of 28 recorded at an operation voltage (V-DD) of 5V. (C) 2015 The Japan Society of Applied Physics
NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge
(2019-01-01)
Chang, Chih-Chcng
;
Wu, Ming-Hung
;
Lin, Jia-Wei
;
Li, Chun-Hsien
;
Parmar, Vivek
Binary STT-MRAM is a highly anticipated embedded non-volatile memory technology in advanced logic nodes <28 nm. How to enable its in-memory computing (IMC) capability is critical for enhancing AI Edge. Based on the soon-available STT-MRAM, we report the first binary deep convolutional neural network (NV-BNN) capable of both local and remote learning. Exploiting intrinsic cumulative switching probability, accurate online training of CIFAR-10 color images (similar to 90%) is realized using a relaxed endurance spec (switching <= 20 times) and hybrid digital/IMC design. For offline training, the accuracy loss due to imprecise weight placement can be mitigated using a rapid non-iterative training-with-noise and fine-tuning scheme.
Submicrometer p-Type SnO Thin-Film Transistors Fabricated by Film Profile Engineering Method
(2019-04-01)
Wu, Ming-Hung
;
Lin, Horng-Chih
;
Li, Pei-Wen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We reported the fabrication of submicrometer p-type tin monoxide (SnO) thin-film transistors (TFTs) with a channel length of 0.2 mu m for back-end-of-line applications using a film profile engineering (FPE) approach. Material analyses indicate that the as-deposited SnO films are amorphous, while be transformed to polycrystalline after a thermal annealing in oxygen ambient. Fabricated p-type SnO FPE-TFTs of a channel length of 0.2 mu m were manifested with ON/OFF current ratio higher than 105 and subthreshold slope of 320 mV/decade, superior to the data of submicrometer SnO devices ever reported. The extracted field-effect mobility is about 0.25 cm(2)/V.s. After ruling out the influence of source/drain series resistance, the intrinsic field-effect mobility is found to be about 1 cm(2)/V.s.
Submicron organic thin-film transistors fabricated by film profile engineering method
(2014-07-28)
Wu, Ming-Hung
;
Lin, Horng-Chih
;
Lin, Hung-Cheng
;
Zan, Hsiao-Wen
;
Meng, Hsin-Fei
In this work, we explore and demonstrate the feasibility of a film profile engineering (FPE) concept in fabricating pentacene-based organic thin-film transistors (OTFTs) with submicron channel length. The FPE scheme utilizes a suspended bridge built on the wafer and the specific deposition conditions to form thin films with desirable profiles. In order to form a continuous pentacene channel under the bridge, the background pressure of thermal evaporator is adjusted by pumping down the filling N-2 to a specific level. The results show that, by setting the deposition pressure at 3 mtorr, functional operations of OTFTs with channel length ranging from 0.4 to 0.6 mu m are obtained. (C) 2014 AIP Publishing LLC.