Browsing by Author "Wu, Shih-Chieh"

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Characterizing fluorine-ion implant effects on poly-Si thin-film transistors with Pr2O3 gate dielectric
(2008-06-01)
Chang, Chia-Wen
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Deng, Chih-Kang
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Wu, Shih-Chieh
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Huang, Jiun-Jia
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Chang, Hong-Ren
The fluorine ion implantation applied to the polycrystalline silicon thin-film transistors (poly-Si TFTs) with high-k. Pr2O3 as gate dielectric is investigated for the first time. Using the Pr2O3 gate dielectric can obtain a high gate capacitance density and thin equivalent-oxide thickness, exhibiting a greatly enhancement in the driving capability of TFT device. Introducing fluorine ions into the poly-Si film by fluorine ion implantation technique can effectively passivate the trap states in the poly-Si film and at the Pr2O3/poly-Si interface to improve the device electrical properties. The Pr2O3 TFTs fabricated on fluorine-implanted poly-Si film exhibit significantly improved electrical performances, including lower threshold voltage, steeper subthreshold swing, higher field-effect mobility, lower off-state leakage current, and higher on/off current ratio, as compared with the control poly-Si Pr2O3 TFTs. Also, the incorporation of fluorine ions also improves the reliability of poly-Si Pr2O3 TFTs against hot-carrier stressing, which is attributed to the formation of stronger Si-F bonds. Furthermore, superior threshold-voltage rolloff characteristic is also demonstrated in the fluorine-implanted poly-Si Pr2O3 TFTs. Therefore, the proposed scheme is a promising technology for high-performance and high-reliability solid-phase crystallized poly-Si TFT.
Design and Optimization Methodology for 3D RRAM Arrays
(2013)
Deng, Yexin
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Chen, Hong-Yu
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Gao, Bin
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Yu, Shimeng
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Wu, Shih-Chieh
3D RRAM arrays are studied at the device-and architecture-levels. The memory cell performance for a horizontal cross-point is shown experimentally to be essentially comparable to vertical pillar-around geometry. Array performances (read/write, energy, and speed) of different 3D architectures are investigated by SPICE simulation, showing horizontal stacked RRAM is superior but suffers from higher bit cost. Adopting a bi-layer pillar electrode structure is demonstrated to enlarge the array size in 3D vertical RRAM. Design guidelines are proposed for the 3D VRRAM: it shows that increasing the number of stacks of VRRAM while keeping the total bits the same, as well as scaling of feature size (F), are critical for reducing RC delay and energy consumption.
Fabrication and Characterization of High-k Dielectric Nickel Titanate Thin Films Using a Modified Sol-Gel Method
(2011-01-01)
Chuang, Shiow-Huey
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Hsieh, Min-Lung
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Wu, Shih-Chieh
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Lin, Hong-Cai
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Chao, Tien-Sheng
This research produced high-quality, single-phase nickel titanate (NiTiO(3)) thin films, a high-k material for gate dielectrics, by a modified sol-gel method. The precursor was prepared by reactions of nickel acetate tetrahydrate and titanium isopropoxide in 2-methoxyethanol with a 1:1 ratio of Ni/Ti in the solution. After coating, the films were post-heat treated between 500 degrees and 900 degrees C. X-ray diffraction indicated that the films deposited at and above 600 degrees C were single-phase nickel titanate. X-ray photoelectron spectra of a typical thin film revealed that the binding energies of Ni 2p(3/2) and Ti 2p(3/2) electrons were 855.2 and 457.7 eV, respectively. Raman spectra showed eight absorptions between 200 and 800 cm-1. Scanning electron microscope images showed smooth surfaces. Findings showed the dielectric constant of the NiTiO(3) film to be 41.36 by capacitance-voltage analysis. The results show that single-phase NiTiO(3) film can be prepared by the sol-gel spin coating method and then heat-treated at 600 degrees C.
Fast Visible-Light Phototransistor Using CVD-Synthesized Large-Area Bilayer WSe2
(2014)
Liu, Pang-Shiuan
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Chen, Chang-Hsiao
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Hsu, Wei-Ting
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Lin, Chih-Pin
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Lin, Tzu-Ping
P-channel transition metal dichalcogenide ultrathin-body phototransistor (UTB-PT) with a response time as fast as 100 mu s has been demonstrated for the first time using the CVD-synthesized large-area bilayer WSe2. Because of its excellent compatibility with mass production, the application of WSe2 UTB-PT for high-speed proximity interactive display has been proposed.
Flexible Three-Bit-Per-Cell Resistive Switching Memory Using a-IGZO TFTs
(2013-10-01)
Wu, Shih-Chieh
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Feng, Hsien-Tsung
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Yu, Ming-Jiue
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Wang, I-Ting
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Hou, Tuo-Hung
This letter proposes a novel high bit density nonvolatile memory using a logic compatible flexible amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) structure fabricated at low temperature. Before electrical forming, the a-IGZO TFT exhibits excellent transistor performance, including an ON/OFF current ratio of 8.8 x 10(6), a steep subthreshold slope of 0.14 V/decade, a threshold voltage of 0.55 V, and a maximum field-effect mobility of 2 cm(2)/Vs. After electrical forming, a three-bit-per-cell resistive switching memory is realized using localized multilevel resistance states at the drain and source bits. Combining dual functionalities to achieve low-cost integration and excellent device characteristics at bending states, the proposed device is promising for future system-on-plastic applications.
Improved Multi-level Control of RRAM Using Pulse-Train Programming
(2014-01-01)
Zhao, Liang
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Chen, Hong-Yu
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Wu, Shih-Chieh
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Jiang, Zizhen
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Yu, Shimeng
Multi-level cell (MLC) capability in RRAM is attractive for reducing the cost per bit. Based on the filamentary switching mechanisms, we propose a pulse-train programming scheme to achieve reliable and uniform MLC controls without the need of any read-verification operation. By applying the novel scheme to a 3 bit/cell RRAM device, the uniformity of resistance distribution can be improved up to 80%.
Low-Cost Embedded RRAM Technology for System-on-Plastic Integration Using a-IGZO TFTs
(2013)
Hou, Tuo-Hung
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Wu, Shih-Chieh
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Yu, Ming-Jiue
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Liu, Pang-Shiuan
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Chi, Li-Jen
This paper discusses the recent progress of a-IGZO TFTs for both high-performance logic and nonvolatile memory applications using an identical device structure, which opens up new opportunities of low-cost embedded memory for system-on-plastic integration. Using localized, independent, and multi-level resistive switching in a-IGZO TFTs, several compact memory array architectures with extremely high bit density have been proposed.
Multi-Bit-per-Cell a-IGZO TFT Resistive-Switching Memory for System-on-Plastic Applications
(2012)
Wu, Shih-Chieh
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Feng, Hsien-Tsung
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Yu, Ming-Jiue
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Wang, I-Ting
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Hou, Tuo-Hung
We reported a novel flexible nonvolatile memory using complete logic-compatible a-IGZO TFTs fabricated at room temperature. The memory device utilized localized and independent resistive switching for high-density two-bit-per-cell and multi-bit-per-cell operations. Combining low-temperature fabrication, low-cost integration, high bit-density, and excellent flexible memory characteristics, this device shows promise for future system-on-plastic applications.
Novel Two-Bit-per-Cell Resistive-Switching Memory for Low-Cost Embedded Applications
(2011-12-01)
Wu, Shih-Chieh
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Lo, Chieh
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Hou, Tuo-Hung
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A novel two-bit-per-cell embedded nonvolatile memory (NVM) device requiring no additional mask and process modification in a logic technology has been proposed using a low-temperature poly-Si thin-film transistor with a HfO(2)/Ni gate stack. The feature of two-bit-per-cell is realized by independent localized resistive switching (RS) at the drain and source bits, respectively, and enables increased bit density over the present single-poly NVM for low-cost embedded applications. Furthermore, minimal degradation of the transistor characteristics after RS allows interchangeable logic/memory operations in an identical device.
Polycrystalline silicon thin-film transistor with nickel-titanium oxide by sol-gel spin-coating and nitrogen implantation
(2012-12-01)
Wu, Shih-Chieh
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Hou, Tuo-Hung
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Chuang, Shiow-Huey
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Chou, Hsin-Chih
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Chao, Tien-Sheng
This study demonstrates polycrystalline silicon thin-film transistors (poly-Si TFTs) integrated with a high-kappa nickel-titanium oxide (NiTiO3) gate dielectric using sol-gel spin-coating and nitrogen channel implantation. This novel fabrication method of the high-kappa NiTiO3 gate dielectric offers thin equivalent-oxide thickness and high gate capacitance density, favorable for increasing the current driving capability. Introducing nitrogen ions into the poly-Si using implantation effectively passivates the trap states not only in the poly-Si channel but also at the gate dielectric/poly-Si interface. The poly-Si NiTiO3 TFTs with nitrogen implantation exhibit significantly improved electrical characteristics, including lower threshold voltage, a steeper subthreshold swing, higher field-effect mobility, a larger on/off current ratio, and less threshold-voltage roll-off. Furthermore, the nitrogen implantation improves the reliability of poly-Si NiTiO3 TFTs against hot-carrier stress and positive bias temperature instability. (C) 2012 Elsevier Ltd. All rights reserved.
Spacer technique to fabricate pSi TFTs with 50nm nanowire channels
(2008)
Chang, Chia-Wen
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Chen, Szu-Fen
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Wu, Shih-Chieh
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Lin, Guan-Liang
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Lei, Tan-Fu
In this work, polycrystalline silicon thin-film transistors (poly-Si TFTs) with 50-nm nanowire (NW) channels fabricated without advanced photolithograph v I v using a sidewall spacer formation technique are proposed for the first time. Because the poly gate electrode is perpendicularly across poly-Si NW channels to form a tri-gate-like structure, the proposed poly-Si NW TFT owns an outstanding gate controllability. In summary, a simple and low-cost scheme is proposed to fabricate high-performance poly-Si NW TFT suitable for future display manufacturing and practical applications.