Browsing by Author "Wu, T. L."

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A Comprehensive Kinetical Modeling of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Energy Effects on Negative Capacitance FETs
(2019-01-01)
Tang, Y-T
;
Fang, C-L
;
Kao, Y-C
;
Modolo, N.
;
Su, C-J
This paper clarifies for the first time the origin of ferroelectricity in the Negative Capacitance Field-Effect Transistors (NCFETs) by molecular dynamics (MD) simulation. MD simulation considering atomic interactions between all atoms enables accurate predictions for the microstructure even at all interfaces. By incorporating the results from MD simulations into a kinetic model, it is able to predict the conditions of crystallization and phase transition during RTP and cooling processes that govern ferroelectricity in FETs. Our simulation reveals that the comparable interfacial energy between o- and t- phase, and in-plane tensile stress from metal capping or interfacial layers (ILs) enable more phase transition from t- to o-phase, and more ferroelectricity in NCFETs. Finally, design methodology to maintain the electric variation of NCFETs is also proposed
Bipolar switching characteristics of low-power Geo resistive memory
(2011-08-01)
Cheng, C. H.
;
Chen, P. C.
;
Liu, S. L.
;
Wu, T. L.
;
Hsu, H. H.
We reported an ultra low-power resistive random access memory (RRAM) combining a low-cost Ni electrode and covalent-bond GeO(x) dielectric. This cost-effective Ni/GeO(x)/TaN RRAM device has very small set power of 2 mu W, ultra-low reset power of 130 pW, greater than 1 order of magnitude resistance window, and stable retention at 85 degrees C. The current flow at low-resistance state is governed by Poole-Frenkel conduction with electrons hopping via defect traps, which is quite different from the filament conduction in metal-oxide RRAM. (C) 2011 Elsevier Ltd. All rights reserved.
High-Performance GaN MOSFET With High-k LaAlO(3)/SiO(2) Gate Dielectric
(2012-01-01)
Tsai, C. Y.
;
Wu, T. L.
;
Chin, Albert
;
電機工程學系
;
Department of Electrical and Computer Engineering
Using a high-k LaAlO(3)/SiO(2) gate dielectric, the recessed-gate GaN MOSFET has a low threshold voltage (V(t)) of 0.1 V, low on-resistance (R(on)) of 13.5 Omega . mm, high breakdown voltage of 385 V, high transconductance (g(m)) of 136 mS/mm, and record-best normalized drive current (mu C(ox)) of 172 mu A/V(2). Such excellent device integrity is due to the small capacitance equivalent thickness of 3.0 nm, using a high-k gate dielectric and recessed-gate etching.
High-Performance GaN MOSFET With High-k LaAlO3/SiO2 Gate Dielectric
(2012-01-01)
Tsai, C. Y.
;
Wu, T. L.
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Using a high-k LaAlO3/SiO2 gate dielectric, the recessed-gate GaN MOSFET has a low threshold voltage (V-t) of 0.1 V, low on-resistance (R-on) of 13.5 Omega . mm, high breakdown voltage of 385 V, high transconductance (g(m)) of 136 mS/mm, and record-best normalized drive current (mu C-ox) of 172 mu A/V-2. Such excellent device integrity is due to the small capacitance equivalent thickness of 3.0 nm, using a high-k gate dielectric and recessed-gate etching.