Browsing by Author "Wu, YCS"

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A simple method for gettering of nickel within the Ni-metal-induced lateral crystallization polycrystalline silicon film
(2006)
Hou, CY
;
Wu, YCS
;
材料科學與工程學系
;
Department of Materials Science and Engineering
Ni-metal-induced lateral crystallization (NILC) of amorphous Si (alpha-Si) has been used to fabricate high-performance low-temperature polycrystalline silicon (poly-Si) thin film transistors (TFTs). The current crystallization technology, however, often leads to trap Ni and NiSi2 precipitates, which degrade the device performance. In this study, we have used alpha-Si films with a thickness of 100 nm as an Ni-gettering layer, silicon-nitride (SiNx) films with a thickness of 30 nm as the etching stop layers and annealed at 550 degrees C for 90 h to reduce the Ni-metal impurity within the NILC poly-Si film. (c) 2006 The Electrochemical Society.
Anomalous electrical performance of nanoscaled interfacial oxides for bonded n-GaAs wafers
(2006-03-13)
Hao, OY
;
Wu, YCS
;
Chiou, HH
;
Liu, CC
;
Cheng, JH
Electrical performance was found to be closely related to the variation of nanosized interface morphology in previous studies. This work investigated in detail the microstructural development of in- and anti-phase bonded interfaces for n-type (100) GaAs wafers treated at 500, 600, 700 and 850 degrees C. The interfacial energy of anti-phase bonding is higher than that of in-phase bonding based on the first-principles calculations. The higher interface energy tends to stabilize the interfacial oxide layer. The continuous interfacial oxide layer observed below 700 degrees C can deteriorate the electrical property due to its insulating property. However, the existence of nanoscaled oxide at anti-phase bonded interfaces can improve the electrical conductivity at 700 degrees C. This is due to the suppression of the evaporation of As atom by the interfacial nanoscaled oxides based on the analysis of autocorrelation function and energy dispersive x-ray spectroscopy. (c) 2006 American Institute of Physics.
Bonding line-patterned In0.5Ga0.5P layer on GaP substrate for the successive growth of high-brightness LED structures
(2005)
Liu, PC
;
Wu, YCS
;
材料科學與工程學系
;
Department of Materials Science and Engineering
The heteroeptixial integration of the III-V semiconductor compound, which was limited by lattice mismatch, can now be accomplished by using the wafer bonding process. In this study, a line-patterned In0.5Ga0.5P layer was successfully transferred to the GaP wafer through the wafer bonding process for the successive growth of high-brightness light-emitting diode (LED) structures. (C) 2004 The Electrochemical Society.
Characterization of excimer-laser-annealed polycrystalline silicon films grown by ultrahigh-vacuum chemical vapor deposition
(2000-10-16)
Chen, YC
;
Wu, YCS
;
Tung, IC
;
Chao, CW
;
Feng, MS
Polycrystalline silicon (poly-Si) films grown by ultrahigh-vacuum chemical vapor deposition (UHVCVD) system and then annealed by excimer laser at room temperature have been investigated for the applications in polycrystalline silicon thin-film transistors (poly-Si TFTs). The results showed that the grain size of the laser-annealed poly-Si film decreased with laser energy density when a lower laser energy density below 157.7 mJ/cm(2) was used. At about the threshold laser energy density (similar to 134.5 mJ/cm(2)), the finest grain structure could be obtained due to the partial melting in the top layer of the film. When the energy density of the excimer laser was larger than the threshold energy density, the large grain growth was initiated. The largest grain structure could be obtained at similar to 184 mJ/cm(2), while its surface roughness was better than that of the nonannealed UHVCVD poly-Si films. The surface roughening was suggested to arise from the specific melt-regrowth process but not the rapid release of hydrogen or capillary wave mechanism derived from laser-annealed amorphous silicon. By use of the laser-annealed UHVCVD poly-Si films as the active layer, the fabricated poly-Si TFT exhibited a field-effect mobility of 138 cm(2)/V s, a subthreshold swing of 0.8 V/dec, a threshold voltage of 3.5 V, and an on/off current ratio of similar to 10(6). (C) 2000 American Institute of Physics. [S0003- 6951(00)03842-0].
Device characteristics of polysilicon thin-film transistors fabricated by electroless plating Ni-induced crystallization of amorphous Si
(2003-04-01)
Chao, CW
;
Wu, YCS
;
Hu, GR
;
Feng, MS
;
材料科學與工程學系
Compared with conventional solid phase crystallized (SPC) thin-film transistors (TFTs), metal-induced laterally crystallized (MILL) TFTs exhibit significantly enhanced performance. Metal films are usually deposited by the physical vapor deposition (PVD) method, which is time-consuming and expensive in terms of equipment cost. In this work, a simpler electroless plating Ni was introduced to replace PVD Ni. It was found that the morphologies and the device characteristics of Ni-induced lateral crystallization TFT were as good as those of PVD Ni-induced lateral crystallization TFT.
Effects of annealing temperature on electrical resistance of bonded n-GaAs wafers
(2004-11-22)
Liu, PC
;
Lu, CL
;
Wu, YCS
;
Cheng, JH
;
Ouyang, H
The electrical characteristics and microstructures of n-type (100) GaAs bonded interfaces were systematically investigated. Experimental results indicated that GaAs did not bond directly to itself, but via an amorphous oxide layer at 400 degreesC. When temperatures increased above 400 degreesC, the oxide bonded area declined and finally disappeared. Electrical resistance decreased with bonding temperature. However, the resistance increased with temperatures exceeding 850 degreesC. (C) 2004 American Institute of Physics.
Effects of tensile stress on growth of Ni-metal-induced lateral crystallization of amorphous silicon
(2005-10-01)
Hou, CY
;
Wu, YCS
;
材料科學與工程學系
;
Department of Materials Science and Engineering
The Ni-metal-induced lateral crystallization (NILC) of amorphous silicon (a-Si) has been used to fabricate low-temperature polycrystalline silicon thin-film transistors. Three stages have been identified in the NILC process: (1) the formation of NiSi(2), precipitates, (2) the nucleation of crystalline Si (c-Si) on NiSi(2) precipitates, and (3) the subsequent migration of NiSi(2) precipitates and growth of c-Si. In this study, a bending fixture was used to investigate the effects of tensile stress oil the growth of NILC. It was found that tensile stress did not enhance NiSi(2) formation and c-Si nucleation stages, but enhanced the c-Si growth stage. It was also found that compressive stress did not change NILC rate.
Electroless plating with Pd induced crystallization of amorphous silicon thin films
(2002-11-01)
Hu, GR
;
Wu, YCS
;
Chao, CW
;
Huang, TJ
;
材料科學與工程學系
A metal-induced crystallization method can be used to decrease the crystallization temperature of amorphous silicon (a-Si). In this study, Pd metal was deposited by an electroless plating method. After it was annealed at 550degreesC, two kinds of needlelike grains were found. The direction of the primary grain was along <211> and the growth of the secondary grain occurred along the <011> direction.
Healing kinetics of interfacial voids in GaAs wafer bonding
(2002-08-19)
Wu, YCS
;
Hu, GZ
;
材料科學與工程學系
;
Department of Materials Science and Engineering
A periodic structure of bonded GaAs wafers has been proposed for quasi-phase-matched second-harmonic generation. After bonding, voids were formed at the interface due to the natural topographical irregularities and contamination on the wafer surface. Within the voids, crystallites with diamond-shaped and dendritic geometries were found, which corresponded to the bonded regions. In this study, artificial voids were introduced at the bonded interface to study the growth kinetics of these crystallites, that is the healing kinetics of these voids. It was found that the crystallite geometries and the growth rates are controlled by the nucleation of new surface layers on the bonded planes, which was the slowest stage during the healing process. (C) 2002 American Institute of Physics.
High-temperature healing of interfacial voids in GaAs wafer bonding
(2002-02-15)
Wu, YCS
;
Liu, PC
;
Feigelson, RS
;
Route, RK
;
材料科學與工程學系
Artificial voids were introduced at bonding interfaces to study how processing parameters affected the healing mechanism of interfacial voids in GaAs wafer bonding. These voids were created by placing unpatterned wafers in contact with topographically patterned wafers. During the bonding process, crystallites formed within these voids and corresponded to bonded regions within the voids. Their formation depended strongly on the height of the surface irregularities at the wafer interfaces. When the void depth (h) was greater than or equal to200 nm, most of the crystallites were diamond shaped. The edges of the diamond features were elongated in the <100> direction. On the other hand, when the void depth was small (hless than or equal to70 nm), dendrites grew quickly in the <110> direction. (C) 2002 American Institute of Physics.
Low temperature polycrystalline silicon thin film transistors fabricated by electroless plating Ni induced crystallization of amorphous Si
(2003)
Chao, CW
;
Wu, YCS
;
Chen, YC
;
Hu, GR
;
Feng, MS
Compared with conventional solid phase crystallized (SPC) thin-film transistors (TFTs), metal-induced laterally crystallized (MILC) TFTs exhibit significantly enhanced performance. Metal films were usually deposited by the physical vapor deposition (PVD) method. In this work, a simpler electroless plating Ni was introduced to replace PVD Ni. It was found that the morphologies and the device characteristics of Ni induced lateral crystallization TFT were as good as those of PVD Ni induced lateral crystallization TFT.
Selective growth of carbon nanotubes on prepatterned amorphous silicon thin films by electroless plating Ni
(2003-09-01)
Chao, CW
;
Wu, YCS
;
Hu, GR
;
Feng, MS
;
材料科學與工程學系
Selective growth of carbon nanotubes (CNTs) synthesized at low temperature by electroless plating Ni was proposed for the first time in this study. After electroless plating, Ni nanoparticles were selectively deposited on the prepatterned amorphous silicon (a-Si) thin films. After plasma-enhanced chemical vapor deposition, well-aligned CNTs were observed only on the Ni-coated a-Si islands. The diameter, density, and the field emission of CNTs could be controlled easily by the Ni plating time. The achievement of controlling the site density and growth area is significant for applications of carbon nanotubes as field emission devices, nanoelectrode arrays, etc. (C) 2003 The Electrochemical Society.
Synthesis of microcrystalline silicon at room temperature using ICP
(2004)
Wu, JH
;
Shieh, JM
;
Dai, BT
;
Wu, YCS
;
材料科學與工程學系
Hydrogenated microcrystalline silicon (muc-Si:H) channel layers were synthesized at a temperature below 100degreesC by inductively coupled plasma (ICP) methods. High ionization efficiency and low ion bombardment from the ICP, enabled the use of high ICP power and, thus, extremely dense plasma or markedly increased electron temperature, promoting the diffusion capability of the reactive radicals that eventually yield ICP muc-Si:H films with large grains of several tens of nanometers, a high deposition rate of 5 Angstrom/s, and a smooth roughness of similar to1 nm. Accordingly, the epitaxial growth of muc-Si:H films at room temperature is demonstrated. (C) 2004 The Electrochemical Society.
The effects of oxygen concentration in Ni film on the metal induced crystallization of amorphous silicon
(2003)
Lin, YD
;
Wu, YCS
;
Chao, CW
;
Hu, GR
;
材料科學與工程學系
The effects of oxygen concentration in Ni film on the metal induced crystallization of amorphous silicon were investigated. It was found that oxygen in Ni deposited film had little effect on the growth rate of polycrystalline silicon. However, an incubation period was needed for nickel oxide to be reduced to nickel metal for the subsequent mediated crystallization process.
The effects of Pd2Si on the electroless plating Pd induced crystallization of amorphous silicon thin films
(2003)
Huang, CTJ
;
Hu, GR
;
Wu, YCS
;
Chao, CW
;
材料科學與工程學系
Electroless plating Pd method has been used to induce crystallization of amorphous silicon through the formation of Pd2Si. Unfortunately, after crystallization, the Pd2Si residues in the Si film degraded the polycrystalline quality. In this study, a two-step annealing process was used to reduce the Pd2Si quantity. Besides, post-RTA treatment was used to improve the quality of poly-Si.
The growth mechanism of micron-size V defects on the hydride vapor phase epitaxy grown undoped GaN films
(2003-05-26)
Lin, PY
;
Wu, YCS
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材料科學與工程學系
;
Department of Materials Science and Engineering
Micron-size V defects were found on the hydride vapor phase epitaxy grown GaN films. When the film thickness increased, the diameter of V defects increased, but the density of the defects decreased. The defect has six {1 1 0 1} facets, which encircle to form a concave hexagonal pyramid. Its shape is similar to that of epitaxial lateral overgrowth (ELO) GaN crystal grown on a dot-patterned GaN underlying layer. Through the analysis of the growth mechanism of ELO GaN, the growth mechanism of the V defects was investigated. (C) 2003 Elsevier Science B.V. All rights reserved.
The influences of contact interfaces between the indium tin oxide-based contact layer and GaN-based LEDs
(2006)
Hsu, CY
;
Lan, WH
;
Wu, YCS
;
材料科學與工程學系
;
Department of Materials Science and Engineering
We have fabricated GaN-based light-emitting diodes (LEDs) using transparent indium tin oxide-based (ITO-based) p contacts. The current-voltage characteristics and life tests of GaN-based LEDs have been studied. LED life tests showed that a pure ITO contact layer had poor reliability at high current stress. We also found that the GaN-based LED could achieve good reliability with a NiO/ITO contact layer. Using transmission electron microscopy and energy-dispersive X-ray spectrometer analyses, we observed In-contained metallic interface between the p-GaN layer and the pure ITO contact layer after annealing at 600 degrees C. It revealed that ITO would react at interface or indiffuse near the interface at 600 C. The LED was degraded with unstable interfaces after life tests (stressed by a 50-mA current injection). To improve the reliability of GaN-based LEDs with the ITO contact layer, we suggest that the NiO layer be used to prevent the reaction and block the leakage pathway. (c) 2006 The Electrochemical Society.
Thermal annealing effect of indium tin oxide contact to GaN light-emitting diodes
(2005-10-01)
Hsu, CY
;
Lan, WH
;
Wu, YCS
;
材料科學與工程學系
;
Department of Materials Science and Engineering
We have fabricated GaN-based light-emitting diodes (LEDs) using transparent indium tin oxide (ITO) for p-type contacts. The current-voltage (I-V) characteristics of the devices have been studied. When annealed at 700 degrees C, the p-n junction of the diodes became very leaky, and even electrical short circuits have been observed. According to scanning electron microscopy (SEM) and energy-dispersive X-ray spectrometer analyses (EDS), it was found that indium (In) diffused into the LED structure with defects such as threading dislocations (TDs) or V-pits. The defects provide leakage paths to cause short circuits in p-n junctions at high annealing temperatures.
Wafer bonding by Ni-induced crystallization of amorphous silicon
(2003-09-01)
Chao, CP
;
Wu, YCS
;
Lee, TL
;
Wang, YH
;
材料科學與工程學系
Wafer bonding by Ni-induced crystallization of amorphous silicon was investigated. It was found that wafers can be bonded through the crystallization of amorphous silicon at temperatures below 550 degreesC. Moreover, when 250 V was applied across the stacked samples, the bonding temperatures could be decreased to as low as 350 degreesC.
Wafer bonding for high-brightness light-emitting diodes via indium tin oxide intermediate layers
(2005-05-01)
Liu, PC
;
Hou, CY
;
Wu, YCS
;
材料科學與工程學系
;
Department of Materials Science and Engineering
A direct wafer-bonding technique has been used to fabricate high-brightness light emitting diodes (LEDs). However, bonding processes were usually performed at elevated temperatures, possibly causing degradation in the quality of the LED structure. In addition to this, misorientation between the two bonded wafers may have caused defects between the wafers. In this study, these two problems were solved by bonding the InGaP/GaAs and GaAs wafers with an indium tin oxide (ITO) polycrystalline film at temperatures below 650 degrees C. It was found that the bonding occurred mainly through the In transport from the InGaP to ITO, and that the electrical resistance decreased with the bonding temperature. (c) 2004 Elsevier B.V. All rights reserved.