Browsing by Author "Wu, Yi-Han"

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ESD Protection Design with Low-Leakage Consideration for Silicon Chips of IoT Applications
(2017-01-01)
Ker, Ming-Don
;
Lin, Chun-Yu
;
Wu, Yi-Han
;
Wang, Wen-Tai
;
電子工程學系及電子研究所
On-chip electrostatic discharge (ESD) protection design with low-leakage consideration for the silicon chips of IoT applications is presented. The proposed ESD protection design uses the fast turn-on silicon-controlled rectifier (SCR) device to implement the power-rail ESD clamp circuit. Experimental results verified in TSMC 28nm CMOS process have shown that the proposed design has advantages of low leakage current (2 similar to 3nA), low trigger voltage (similar to 2V), high ESD robustness (>8kV), and free to latchup issue.
Low-Leakage and Low-Trigger-Voltage SCR Device for ESD Protection in 28-nm High-k Metal Gate CMOS Process
(2016-11)
Lin, Chun-Yu
;
Wu, Yi-Han
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
To effectively protect integrated circuits from electrostatic discharge (ESD) damage, this letter proposes a silicon-controlled rectifier (SCR) device with low trigger voltage, low leakage current, low parasitic capacitance, and which requires no additional process step. The proposed device uses two metal gates to separate the anode and cathode of the SCR to reduce the leakage current. These two gates are well controlled to trigger the SCR device. The test devices have been implemented and verified in a 28-nm high-k metal gate CMOS process. Experimental results show that the proposed SCR exhibits a low trigger voltage (<3 V), low leakage current (<5 nA), low parasitic capacitance (<40 fF), and sufficient ESD robustness (>1 kV in human-body-model tests). Based on its good performances during ESD stress and normal circuit operating conditions, the proposed SCR device is very suitable for ESD protection in advanced CMOS processes.