Browsing by Author "Wu, Yi-Hong"

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A Novel p-n-Diode Structure of SONOS-Type TFT NVM With Embedded Silicon Nanocrystals
(2010-11-01)
Chiang, Tsung-Yu
;
Ma, William Cheng-Yu
;
Wu, Yi-Hong
;
Wang, Kuan-Ti
;
Chao, Tien-Sheng
In this letter, for the first time, a novel p-n-diode (PND) structure of SONOS-type thin-film transistor (TFT) nonvolatile memory (NVM) with embedded silicon nanocrystals (Si-NCs) in the silicon nitride layer using an in situ method is successfully demonstrated. This novel structure has many advantages, including high density and suitability for 3-D circuit integration. Hot-electron injection and hot-hole injection are used as the program and erase methods, respectively. The sensing current of the three-terminal PND-TFT NVM is 10(-7) A by the band-to-band tunneling current. A much larger memory window (> 12 V) and good data retention time (> 10(8) s for 12% charge loss) are exhibited. The device appears to have great potential for system-on-panel applications.
A Novel p-n-Diode Structure of SONOS-Type TFT NVM With Embedded Silicon Nanocrystals
(2010-11-01)
Chiang, Tsung-Yu
;
Ma, William Cheng-Yu
;
Wu, Yi-Hong
;
Wang, Kuan-Ti
;
Chao, Tien-Sheng
In this letter, for the first time, a novel p-n-diode (PND) structure of SONOS-type thin-film transistor (TFT) nonvolatile memory (NVM) with embedded silicon nanocrystals (Si-NCs) in the silicon nitride layer using an in situ method is successfully demonstrated. This novel structure has many advantages, including high density and suitability for 3-D circuit integration. Hot-electron injection and hot-hole injection are used as the program and erase methods, respectively. The sensing current of the three-terminal PND-TFT NVM is 10(-7) A by the band-to-band tunneling current. A much larger memory window (> 12 V) and good data retention time (> 10(8) s for 12% charge loss) are exhibited. The device appears to have great potential for system-on-panel applications.
Characteristics of PBTI and hot carrier stress for LTPS-TFT with high-kappa gate dielectric
(2008-02-01)
Ma, Ming-Wen
;
Chen, Chih-Yang
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Wu, Yi-Hong
In this letter, the characteristics of positive bias temperature instability (PBTI) and hot carrier stress (HCS) for the low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO2 gate dielectric are well investigated for the first time. Under room temperature stress condition, the PBTI shows a more serious degradation than does HCS, indicating that the gate bias stress would dominate the hot carrier degradation behavior for HfO2 LTPS-TFT. In addition, an abnormal behavior of the I-min degradation with different drain bias stress under high-temperature stress condition is also observed and identified in this letter. The degradation of device's performance under high-temperature stress condition can be attributed to the damages of both the HfO2 gate dielectric and the poly-Si grain boundaries.
Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals
(2010-08-01)
Chiang, Tsung-Yu
;
Wu, Yi-Hong
;
Ma, William Cheng-Yu
;
Kuo, Po-Yi
;
Wang, Kuan-Ti
In this paper, silicon-oxide-nitride-oxide-semiconductor (SONOS) devices with embedded silicon nanocrystals (Si-NCs) in silicon nitride using in situ method with multilevel and 2-b/cell operation have been successfully demonstrated. The proposed in situ Si-NC deposition method exhibits the advantages of low cost, simplicity, and compatibility with modern IC processes. SONOS memories with embedded Si-NCs exhibit a significantly improved performance with a large memory window (> 5.5 V), low operating voltage (P/E voltage: V(g) = 6 V, V(d) = 7 V and V(g) = -7 V, V(d) = 10 V, respectively), greater tolerable gate and drain disturbance (V(t) shift < 0.2 V), negligible second-bit effect, high P/E speed (after programming time = 10 mu s with a 2-V shift of V(t) under V(g) = V(d) = 6 V operation), good retention time (> 10(8) s for 13% charge loss), and excellent endurance performance (after 10(4) P/E cycles with a memory window of 3 V).
High-Performance Poly-Si Thin-Film Transistors With L-Fin Channels
(2012-02-01)
Lu, Yi-Hsien
;
Kuo, Po-Yi
;
Lin, Je-Wei
;
Wu, Yi-Hong
;
Chen, Yi-Hsuan
For the first time, we construct poly-Si thin-film transistors (TFTs) with novel L-shaped poly-Si fin channels (poly-Si TFTs with L-fin channels, called LFin-TFTs). The L-fin channels of LFin-TFTs are similar to the multiple-gated fin channels of FinFETs. The LFin-TFTs exhibit a low supply gate voltage (3 V), a good subthreshold swing (SS) similar to 190 mV/dec, and a high on/off current ratio (I-ON/I-OFF) > 10(6) (V-D = 1 V) without hydrogen-related plasma treatments. After Ni salicidation, the devices exhibit steep SS similar to 148 mV/dec and I-ON/I-OFF similar to 10(7). After NH3 plasma treatment, the characteristics of the devices are further improved. The LFin-TFTs have steeper SS similar to 132 mV/dec, higher I-ON/I-OFF > 10(7), and threshold voltage (V-TH) similar to 0.036 V.
High-program/erase-speed SONOS with in situ silicon nanocrystals
(2008-10-01)
Chiang, Tsung-Yu
;
Chao, Tien-Sheng
;
Wu, Yi-Hong
;
Yang, Wen-Luh
;
電子物理學系
In this letter, for the first time, we have successfully fabricated silicon-oxide-nitride-oxide-silicon (SONOS) devices with embedded silicon nanocrystals (Si-NCs) in silicon nitride using in situ method. This process is simple and compatible to modern IC processes. Different Si-NCs deposition times by in situ method were investigated at first. SONOS devices with embedded Si-NCs in silicon nitride exhibit excellent characteristics in terms of larger memory windows (> 5.5 V), lower operation voltage, high P/E speed, and longer retention time (> 10(8) s for 13% charge loss).
High-Speed Multilevel Wrapped-Select-Gate SONOS Memory Using a Novel Dynamic Threshold Source-Side-Injection (DTSSI) Programming Method
(2009-06-01)
Wang, Kuan-Ti
;
Chao, Tien-Sheng
;
Wu, Woei-Cherng
;
Chiang, Tsung-Yu
;
Wu, Yi-Hong
A. high programming speed with a low-power-consumption wrapped-select-gate poly-Si-oxide-nitride-oxide-silicon memory is successfully demonstrated using the novel dynamic threshold source-side-injection programming technique. The select gate embedded in such particular memory structure acts like a dynamic MOSFET resulting in programming current (I(PGM)) that can be enhanced in this DT mode, easily attaining a high programming speed of about 100 ns. It still doubles the memory density by achieving the 2-bit/cell operation with MLC under DT mode.
Impacts of fluorine ion implantation with low-temperature solid-phase crystallized activation on high-kappa LTPS-TFT
(2008-02-01)
Ma, Ming-Wen
;
Chen, Chih-Yang
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Wu, Yi-Hong
In this letter, fluorine ion implantation with low-temperature solid-phase crystallized activation scheme is used to obtain a high-performance HfO2 low-temperature poly-Si thin-film transistor (LTPS-TFT) for the first time. The secondary ion mass spectrometer (SIMS) analysis shows a different fluorine profile compared to that annealed at high temperature. About one order current reduction of I-min is achieved because 25% grain-boundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO2 gate dielectric and fluorine preimplantation can simultaneously achieve low V-TH similar to 1.32 V, excellent subthreshold swing similar to 0.141 V/dec, and high I-ON/I-min current ratio 1.98 x 10(7).
MILC-TFT With High-kappa Dielectrics for One-Time-Programmable Memory Application
(2009-09-01)
Chiang, Tsung-Yu
;
Ma, Ming-Wen
;
Wu, Yi-Hong
;
Kuo, Po-Yi
;
Wang, Kuan-Ti
In this letter, for the first time, one-time-programmable (OTP) memory fabricated on the low-temperature poly-Si p-cbannel thin-film transistor (TFT) with metal-induced lateral-crystallization channel layer and high-kappa dielectrics is demonstrated. The state of this OTP memory can be identified by the scheme of gate-induced drain leakage current measurement. The OTP-TFT memory has good electrical characteristics in terms of low threshold voltage V(th) similar to -0.78 V, excellent subthreshold swing similar to 105 mV/dec, low operation voltage, faster programming speeds, and excellent reliability characteristics.
Novel 2-Bit/Cell Wrapped-Select-Gate SONOS TFT Memory Using Source-Side Injection for NOR-Type Flash Array
(2012-06-01)
Wang, Kuan-Ti
;
Hsueh, Fang-Chang
;
Lu, Yu-Lun
;
Chiang, Tsung-Yu
;
Wu, Yi-Hong
This letter is the first to successfully demonstrate the 2-bit/cell wrapped-selected-gate (WSG) SONOS thin-film transistor (TFT) memory using source-side injection (SSI). Because of the higher programming efficiency of SSI, a memory window of approximately 3 V can be easily achieved in 10 mu s and 30 ms for the program and erase modes, respectively. In addition, we performed an excellent 2-bit/cell distinguish margin for 3-V memory window in WSG-SONOS TFT memory. The optimal reliability of the endurance and data retention tests can be executed by adjusting the applied voltage appropriately.
Novel Sub-10-nm Gate-All-Around Si Nanowire Channel Poly-Si TFTs With Raised Source/Drain
(2011-02-01)
Lu, Yi-Hsien
;
Kuo, Po-Yi
;
Wu, Yi-Hong
;
Chen, Yi-Hsuan
;
Chao, Tien-Sheng
We have successfully fabricated novel sub-10-nm gate-all-around Si nanowire (NW) poly-Si TFTs with raised source/drain structure (GAA RSDNW-TFTs). The Si NW dimension is about 7 x 12 nm. A superior smooth elliptical shape is obtained, for the first time, in the category of poly-Si NW TFTs through the use of a novel fabrication process requiring no advanced lithographic tools. The GAA RSDNW-TFTs exhibit low supply gate voltage (3 V), steep subthreshold swing similar to 99 mV/dec, and high I(ON)/I(OFF) > 10(7) (V(D) = 1 V) without hydrogen-related plasma treatments. Furthermore, the DIBL of GAA RSDNW-TFTs is well controlled. These improvements can be attributed to the 3-D gate controllability, raised S/D structure, and sub-10-nm Si NW channel. These novel GAA RSDNW-TFTs are, thus, quite suitable for system-on-panel and 3-D IC applications.
Novel Symmetric Vertical-Channel Ni-Salicided Poly-Si Thin-Film Transistors With High ON/OFF-Current Ratio
(2010-11-01)
Wu, Yi-Hong
;
Kuo, Po-Yi
;
Lu, Yi-Hsien
;
Chen, Yi-Hsuan
;
Chao, Tien-Sheng
We have successfully fabricated the symmetric vertical-channel Ni-salicided polycrystalline silicon thin-film transistors (VSA-TFTs) for the first time. The transfer characteristics of VSA-TFTs show a sharp turning between subthreshold and ON state. The OFF-state currents can be improved by a modified overetching of oxide, equivalent dual-gate structure, and n(+) floating-region length. The ON-state currents can be enhanced by Ni-salicidation. The VSA-TFTs display a good subthreshold swing of 220 mV/dec, steep mobility increase (field-effect mobility of 76 cm(2)/ V . s), and large ON/OFF-current ratio of more than 109 (I(OFF) = 4 x 10 (14), I(ON) = 7 x 10 (5), and W(mask)/L(mask) = 10 mu m/3 mu m).
Physical Mechanism of High-Programming-Efficiency Dynamic-Threshold Source-Side Injection in Wrapped-Select-Gate SONOS for NOR-Type Flash Memory
(2009-11-01)
Wang, Kuan-Ti
;
Chao, Tien-Sheng
;
Chiang, Tsung-Yu
;
Wu, Woei-Cherng
;
Kuo, Po-Yi
For the first time, a programming mechanism for conventional source-side injection (SSI) (normal mode), substrate-bias enhanced SSI (body mode), and dynamic-threshold SSI (DTSSI) (DT mode) of a wrapped-select-gate SONOS memory is developed with 2-D Poisson equation and hot-electron simulation and programming characteristic measurement for NOR Flash memory. Compared with traditional SSI, DTSSI mechanisms are determined in terms of lateral acceleration electric field and programming current (I(PGM)) in the neutral gap region, resulting in high programming efficiency. Furthermore, the lateral electric field intersects the vertical electric field, indicating that the main charge injection point is from the end edge of the gap region close to the word gate.
Reliability Analysis of Symmetric Vertical-Channel Nickel-Salicided Poly-Si Thin-Film Transistors
(2012-08-01)
Wu, Yi-Hong
;
Lin, Je-Wei
;
Lu, Yi-Hsien
;
Kuo, Rou-Han
;
Yen, Li-Chen
"In this paper, a reliability analysis of symmetric Vertical-channel Ni-SAlicided poly-Si thin-film transistors (VSA-TFTs) is performed for the first time. First, we compare the drain-induced barrier-lowering effect (DIBL) of VSA-TFTs. The VSA-TFTs with thinner gate oxide thickness, an offset structure, and a longer floating n(+) region have better immunity to DIBL. Second, VSA-TFTs with a longer floating n(+) region also have better immunity under hot-carrier (HC) stress and self-heating (SH) stress. However, VSA-TFTs with a shorter floating n(+) region also have better immunity to positive gate bias (PGB) stress. Consequently, in order to optimize reliability characteristics, including SH stress, HC stress, and PGB stress, it is necessary to modulate the length of the floating n(+) region. Third, the PGB stress, rather than SH stress or HC stress, becomes a major issue for VSA-TFTs under the stress bias below 4 V. In other words, PGB stress will dominate the degradation behaviors when the stress bias is not high enough to achieve SH stress and HC stress. Finally, the worst degradation condition of VSA-TFTs under HC stress, similar to that of most TFT devices, occurs when the stress of V-G is less than half of V-D"
SONOS memories with embedded silicon nanocrystals in nitride
(2008-07-01)
Liu, Mei-Chun
;
Chiang, Tsung-Yu
;
Kuo, Po-Yi
;
Chou, Ming-Hong
;
Wu, Yi-Hong
We have successfully demonstrated SONOS memories with embedded Si-NCs in silicon nitride. This new structure exhibits excellent characteristics in terms of larger memory windows and longer retention time compared to control devices. Using the same thickness 2.5 nm of the bottom tunneling oxide, we found that N(2)O is better than O(2) oxide. Retention property is improved when the thickness of N(2)O is increased to 3.0 nm.
SONOS memories with embedded silicon nanocrystals in nitride by In-situ deposition method
(2008)
Wu, Yi-Hong
;
Chiang, Tsung-Yu
;
Liu, Sheng-Hsien
;
Yang, Wen-Luh
;
Chao, Tien-Sheng
In this work, we have successfully demonstrated SONOS memories with embedded Si-NCs in silicon nitride by In-situ deposition method. The self-assembly silicon nanocrystals were in-situ deposited within the Si3N4 storage layer by dissociation of dichlorosilane (SiH2Cl2) gas to a high density of 9 x 10(11) cm(-2). This new structure exhibits larger memory windows for up to 6 V, better program/erase characteristics, and excellent data retention properties as compared to control device. In addition, this novel process is simple, low cost, and compatible to the standard complementary metal-oxide-semiconductor (CMOS) processes. This technology seems to be very promising for the advanced flash memory devices.
Symmetric Vertical-Channel Nickel-Salicided Poly-Si Thin-Film Transistors With Self-Aligned Oxide Overetching Structures
(2011-07-01)
Wu, Yi-Hong
;
Kuo, Po-Yi
;
Lu, Yi-Hsien
;
Chen, Yi-Hsuan
;
Chiang, Tsung-Yu
This paper reports the impacts of NH(3) plasma treatment time, oxide overetching depth, and gate oxide thickness on symmetric vertical-channel Ni-salicided poly-Si thin-film transistors (VSA-TFTs) for the first time. OFF-state currents may be improved by increasing the oxide overetching depth. The ON/OFF current ratio may be also improved by increasing the oxide overetching depth. The NH(3) plasma optimum treatment time of VSA-TFTs is significantly shorter than that of conventional top-gate horizontal-channel TFTs. The performance of VSA-TFTs is degraded by NH(3) plasma treatment for too long a time. VSA-TFTs with 15-nm gate oxide thickness display better subthreshold swing (< 150 mV/dec) than VSA-TFTs with 30-nm gate oxide thickness. OFF-state currents can be improved by increasing L(mask), even when the oxide overetching depth and the gate oxide thickness are changed.