Browsing by Author "YANG, YH"
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Item type:Item, A NEW APPROACH TO MODEL CMOS LATCHUP(1985)Item type:Item, A NEW CRITERION FOR TRANSIENT LATCHUP ANALYSIS IN BULK CMOS(1989-07-01)Item type:Item, A NEW METHOD FOR DETERMINING THE TERMINAL SERIES RESISTANCES AND HIGH-INJECTION COEFFICIENT OF BIPOLAR-TRANSISTORS IN CMOS INTEGRATED-CIRCUITS FOR COMPUTER-AIDED CIRCUIT MODELING(1988-05-01)Item type:Item, ANALYSIS AND MODELING OF INITIAL DELAY TIME AND ITS IMPACT ON PROPAGATION DELAY OF CMOS LOGIC GATES(1989-10-01)Item type:Item, THE EFFECT OF LAYOUT, SUBSTRATE WELL BIASES, AND TRIGGERING SOURCE LOCATION ON LATCHUP TRIGGERING CURRENTS IN BULK CMOS CIRCUITS(1989-04-01)