Browsing by Author "Yang, Fu-Liang"

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3D 65nm CMOS with 320 degrees C Microwave Dopant Activation
(2009)
Lee, Yao-Jen
;
Lu, Yu-Lun
;
Hsueh, Fu-Kuo
;
Huang, Kuo-Chin
;
Wan, Chia-Chen
For the first time, CMOS TFTs of 65nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is. demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF2 for p-MOS TFTs and P-31 for n-MOS TFTs at a low temperature of 320 degrees C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.
3D Ferroelectric-like NVM/CMOS Hybrid Chip by sub-400 degrees C Sequential Layered Integration
(2012-01-01)
Lien, Yu-Chung
;
Shieh, Jia-Min
;
Huang, Wen-Hsien
;
Hsieh, Wei-Shang
;
Tu, Cheng-Hui
For the first time, a sequentially processed 3D hybrid chip is demonstrated by stacking low-temperature (LT) Ferroelectric-like (FE-like) metal-oxide nonvolatile memory (NVM) and CMOS. The high-mobility (333 and 113 cm(2)/V-s) and low-subthreshold swing (97 and 112 mV/decade) N/P-type thin film transistors (TFTs) construct stacked inverters showing sharp transfer characteristic as the fundamental element of CMOS array and stacked 3D NVMs. The sequential layered integration is enabled by cutting-edge low thermal-budget plasma/laser processes and self-assembled FE-like metal-oxide materials. The implementation of sub-400 degrees C new-type metal-ion (Eu+3)-mediated atomic-polar-structured (Eu+3-APS) dielectric realizes stackable FE-like NVMs with program speed of 100 nanosecond, toward future 3D layered CMOS with giant high-speed dat-storage application era.
A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications
(2012-04-01)
Chen, Min-Cheng
;
Chen, Hao-Yu
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Lin, Chia-Yi
;
Chien, Chao-Hsin
;
Hsieh, Tsung-Fan
This paper reports a versatile nano-sensor technology using "top-down" poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording.
A Comprehensive Study of Ge1-xSix on Ge for the Ge nMOSFETs with Tensile Stress, Shallow Junctions and Reduced Leakage
(2009)
Luo, Guang-Li
;
Huang, Shih-Chiang
;
Chung, Cheng-Ting
;
Heh, Dawei
;
Chien, Chao-Hsin
For the first time, growth of high-quality Ge-rich Ge1-xSix (0 <= x <= 0.14) layers on Ge substrate was demonstrated. An effective suppression of the phosphorus diffusion in Ge1-xSix and a better thermal stability of the nickel germanide on Ge1-xSix were observed. A higher rectifying ratio with a reduced diode leakage current in n(+)-Ge1-xSix/p-Ge1-xSix is compared with n(+)-Ge/p-Ge. These results indicate that it is suitable for Ge1-xSix to be used as source/drain (S/D) to fabricate the uniaxial tensile-strained channel Ge nMOSFETs.
A Novel Nanoinjection Lithography (NInL) Technology and Its Application for 16-nm Node Device Fabrication
(2011-11-01)
Chen, Hou-Yu
;
Chen, Chun-Chi
;
Hsueh, Fu-Kuo
;
Liu, Jan-Tsai
;
Shy, Shyi-Long
For more than 45 years, photon-and electron-sensitive materials have been used to produce pattern-transfer masks in the lithographic manufacturing of integrated circuits. With the semiconductor technology feature size continuing to shrink and the requirements of low-variability and low-cost manufacturing, optical lithography is driven to its limits. In this paper, we report a novel nanoinjection lithography (NInL) technique that employs electron-beam-assisted deposition to form pattern-transfer hard mask in a direct-write deposit approach. By scanning the 4.6-nm-diameter electron beam while injecting a suitable organometallic precursor gas around the location of e-beam and just above the substrate, we form a high-density (pitch: 40 nm) high-uniformity (3-sigma linewidth roughness: 2 nm) hard mask for subsequent etching without using proximity-effect correction techniques. Furthermore, this technique can also directly deposit a metal pattern for interconnect or a dielectric pattern without the need for separate metal or dielectric deposition, photoresist etch-mask, and etching processes. The NInL approach simplifies the hard-mask creation or even metal or dielectric pattern creation process modules from five or tens of steps to only a single step. Therefore, it saves both photomask making and wafer processing costs. In addition, room-temperature NInL deposition of conductor/dielectric materials enables the fabrication of small versatile devices and circuits. For demonstration, we fabricated a functional 16-nm six-transistor static random access memory (SRAM) cell (area: occupying only 0.039 mu m(2)), 43% the size of the smallest previously reported SRAM cell, using the FinFET structure and a dynamic V(dd) regulator approach. The NInL technique offers a new way of exploring low-volume high-value 16-nm complementary metal-oxide-semiconductor (CMOS) devices and circuit designs with minimal additional investment and obtains early access to extreme CMOS scaling.
A Numerical Study of Si-TMD Contact with n/p Type Operation and Interface Barrier Reduction for Sub-5 nm Monolayer MoS2 FET
(2016-01-01)
Tang, Ying-Tsan
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Li, Kai-Shin
;
Li, Lain-Jong
;
Li, Ming-Yang
;
Lin, Chang-Hsien
An atomic-scale numerical study of Si contact with transition metal dichalcogenides (TMD) semiconductor materials is proposed by first-principles simulation for the first time. The monolayer MoS2 channel can be operated as both of n- and p-type FET by properly doping Si S/D to adjust the TMD channel potential. The gradient MoSx junction of dichalcogenide vacancies enables Si-MoS2 contact resistance lower than 100 Omega-mu m for interface Schottky barrier height reduction. The compact Si-MoS2 interface study can potentially provide monolayer TMD contact design guideline for the sub-5 nm TMD FET fabrication technology.
Characteristic fluctuation dependence on discrete dopant for 16nm SOI FinFETs at different temperature
(2007)
Li, Yiming
;
Hwang, Chih-Hong
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Yu, Shao-Ming
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Huang, Hsuan-Ming
;
Yeh, Ta-Ching
In this paper, we numerically study the discrete-dopant-induced characteristic fluctuations in 16nnn silicon-on-insulator (SOI) FinFETs. For devices under different temperature condition, discrete dopants are statistically generated and positioned into the three-dimensional channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". Electrical characteristics' fluctuations are growing worse when the substrate temperature increases, the standard deviation of threshold voltage increases 1.75 times when substrate temperature increases from 300K to 400K for example. This "atomistic" device simulation technique is computationally cost-effective and provides us an insight into the problem of discrete-dopant-induced fluctuation and the relation between the fluctuation and thermal effect.
CIGS solar cell integrated with high mobility microcrystalline Si TFTs on 30X40 cm(2) glass panels for self powered electronics
(2012-01-01)
Shen, Chang-Hong
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Shieh, Jia-Min
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Wu, Tsung-Ta
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Huang, Jung Y.
;
Huang, Che-Hsuan
For the first time, we report a novel self-powered TFT panel (30X40cm(2)) by integration of sputtering/non-toxic Se vapor selenization copper-indium-gallium-selenide (CIGS) solar cell (conversion efficiency of 8%) and high electron-mobility (172 cm(2)/V-s) micro-crystalline (mu c)-Si TFTs.
Discrete dopant fluctuated 20nm/15nm-gate planar CMOS
(2007)
Yang, Fu-Liang
;
Hwang, Jiunn-Ren
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Chen, Hung-Ming
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Shen, Jeng-Jung
;
Yu, Shao-Ming
We have, for the first time, experimentally quantified random dopant distribution (RDD) induced V-t standard deviation up to 40mV for 20nm-gate planar CMOS. Discrete dopants have been statistically positioned in the 3D channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". As gate length further scaling down to 15nm, the newly developed discrete-dopant scheme features an effective solution to suppress 3-sigma-edge single digit dopants induced V-t variation by gate work function modulation. The extensive study may postpone the scaling limit projected for planar CMOS.
Discrete dopant fluctuations in 20-nm/15-nm-gate planar CMOS
(2008-06-01)
Li, Yiming
;
Yu, Shao-Ming
;
Hwang, Jiunn-Ren
;
Yang, Fu-Liang
;
資訊工程學系
We experimentally quantified, for the first time, the random dopant distribution (RDD)-induced threshold voltage (V-t) standard deviation up to 40 mV for 20-nm-gate planar complementary metal-oxide-semiconductor (CMOS) field-effect transistors. Discrete dopants have been statistically positioned in the 3-D channel region to examine the associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation." As the gate length further scales down to 15 nm, the newly developed discrete dopant scheme features an effective solution to suppress the 3-sigma-edge single-digit dopant-induced V-t variation by the gate work function modulation. The results of this paper may postpone the scaling limit projected for planar CMOS.
Effect of top electrode material on resistive switching properties of ZrO2 film memory devices
(2007-05-01)
Lin, Chih-Yang
;
Wu, Chen-Yu
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Wu, Chung-Yi
;
Lee, Tzyh-Cheang
;
Yang, Fu-Liang
The influence of top electrode material on the resistive switching properties of ZrO2 -based memory film using Pt as a bottom electrode was investigated in this letter. In comparison with Pt/ZrO2/Pt and Al/ZrO2/Pt devices, the Ti/ZrO2/Pt device exhibits different resistive switching current-voltage (I-V) curve, which can be traced and reproduced by a dc voltage more than 1000 times only showing a little decrease of resistance ratio between high and low resistance states. Furthermore, the broad dispersions of resistive switching characteristics in the Pt/ZrO2/Pt and Al/ZrO2/Pt devices are generally observed during successive resistive switching, but those dispersions are suppressed by the device using Ti as a top electrode. The reliability results, such as cycling endurance and continuous readout test, are also presented. The write-read-erase-read operations can be over 104 cycles without degradation. No data loss is found upon successive readout after performing various endurance cycles.
Electrical characteristic fluctuations in sub-45nm CMOS devices
(2006)
Yang, Fu-Liang
;
Hwang, Jiunn-Ren
;
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
Random fluctuations of electrical characteristics in sub-45nm CMOS devices introduced by process-parameter variations through severe short channel effects have made the scaling of conventional planar transistors much more difficult than ever before, especially while further reduction of gate dielectric thickness is ambiguous. In this paper, we systematically investigate the fluctuations of threshold voltages at varied gate length, considering the effects of channel doping, gate dielectric thickness, and new transistor structures such as thin-buried-oxide SOI and FinFETs. Quantitative analysis is undertaken in terms of three major variation sources: random doping distribution, gate length deviation, and line edge roughness. The analysis also features a low V-t-fluctuation transistor for 16nm node achieved with undoped body, mid-gap metal gate, and nanowire channel.
Estimating the Detection Stability of a Si Nanowire Sensor Using an Additional Charging Electrode
(2013)
Chen, Min-Cheng
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Chen, Hsiao-Chien
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Lee, Ta-Hsien
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Lin, Yu-Hsien
;
Shih, Jyun-Hung
This paper proposes a sensing stability estimation method that involves using an additional forcing electrode to simulate the surface charge coupling effect for bottom gate nanowire sensors. The alteration of the Si nanowire can be observed by using the charging electrode without any complex surface treatment and micro-channel setup. The nanowire sensor has a distinct charge-sensitive slope (V-th shift > 60 mV/10(-16)C) with a wire-width scaling of 35 nm. The proposed estimation technique simplifies the charge sensing operation.
Fast programming metal-gate Si quantum dot nonvolatile memory using green nanosecond laser spike annealing
(2012-04-02)
Lien, Yu-Chung
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Shieh, Jia-Min
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Huang, Wen-Hsien
;
Tu, Cheng-Hui
;
Wang, Chieh
The ultrafast metal-gate silicon quantum-dot (Si-QD) nonvolatile memory (NVM) with program/erase speed of 1 mu s under low operating voltages of +/-7V is achieved by thin tunneling oxide, in situ Si-QD-embedded dielectrics, and metal gate. Selective source/drain activation by green nanosecond laser spike annealing, due to metal-gate as light-blocking layer, responds to low thermal damage on gate structures and, therefore, suppresses re-crystallization/deformation/diffusion of embedded Si-QDs. Accordingly, it greatly sustains efficient charge trapping/de-trapping in numerous deep charge-trapping sites in discrete Si-QDs. Such a gate nanostructure also ensures excellent endurance and retention in the microsecond-operation Si-QD NVM. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.3700729]
Heterogeneously integrated sub-40nm low-power epi-like Ge/Si monolithic 3D-IC with stacked SiGeC ambient light harvester
(2014)
Shen, Chang-Hong
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Shieh, Jia-Min
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Huang, Wen-Hsien
;
Wu, Tsung-Ta
;
Chen, Chien-Fu
For the first time, we report heterogeneously integrated sub-40nm epi-like Ge/Si monolithic 3D-IC with low-power logic/NVM circuits and efficient photovoltaic energy harvester. Threshold voltage engineering and driving current boosting technologies enable stackable Ge/Si UTB (< 15nm) MOSFETs, CMOS inverter and SRAM (SNM=270mV@0.7V) achieve low operation voltage. Stackable 1-T NVM with high speed (100ns) and low driving-voltage operation provide power-off storage while SRAM serve as power-on working memory. 100% aperture ratio SiGeC ambient light energy harvester with maximum output power of 7mW/cm(2) layered on the monolithic 3D-IC chip envisions a self-powered monolithic 3D-IC technology for advanced low-power wire-less sensor networks, wearable devices, and devices for Internet of Things.
Hybrid Si/TMD 2D Electronic Double Channels Fabricated Using Solid CVD Few-Layer-MoS2 Stacking for V-th Matching and CMOS-Compatible 3DFETs
(2014)
Chen, Min-Cheng
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Lin, Chia-Yi
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Li, Kai-Hsin
;
Li, Lain-Jong
;
Chen, Chang-Hsiao
Stackable 3DFETs such as FinFET using hybrid Si/MoS 2 channels were developed using a fully CMOS-compatible process. Adding several molecular layers (3-16 layers) of the transition-metal dichalcogenide (TMD), MoS2 to Si fin and nanowire resulted in improved (+25%) I-on,I-n of the FinFET and nanowire FET (NWFET). The PFETs also operated effectively and the N/P device V-th are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics.
Inductively coupled plasma grown semiconductor films for low cost solar cells with improved light-soaking stability
(2011-07-18)
Shen, Chang-Hong
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Shieh, Jia-Min
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Huang, Jung Y.
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Kuo, Hao-Chung
;
Hsu, Chih-Wei
We investigate the performance of a single-junction amorphous Si (a-Si) solar cell fabricated with inductively coupled plasma (ICP) deposition technique. The high-density plasma resulting from high dissociation capacity of ICP enables good-quality hydrogenated Si films to be synthesized at low temperatures. High-density ICP also promotes the diffusion of reactive radicals on substrates and forms a-Si:H films with low defect density (similar to 3 x 10(15) cm(-3)). We demonstrate single-junction a-Si solar cells with a conversion efficiency of 9.6% and improved light-soaking stability. This low thermal-budget thin-film technique could open up the feasibility of efficient thin film solar cells on flexible substrates. (C) 2011 American Institute of Physics. [doi:10.1063/1.3615650]
Low Temperature a-SiGe:H Near-IR Sensor and Photovoltaic Devices for Flexible Multi-functional Panel
(2013-01-01)
Kao, Ming-Hsuan
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Shieh, Jia-Min
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Shen, Chang-Hong
;
Yu, Peichen
;
Kuo, Hao-Chung
High Near-IR response photo-diode (0.1A/W@800nm) and high efficiency a-Si/a-SiGe tandem solar cell (8.38%) were demonstrated using high-density plasma-fabricated a-SiGe:H deposition technology with Si2H6 and GeH4 precursor. The low temperature (140 degrees C) a-SiGe: H films with low defect density (2.3x10(16)cm(-3)) are suitable for the applications of flexible solar self-powered multi-functional panel and 3D stacked monolithic devices.
Low-Temperature Microwave Annealing Processes for Future IC Fabrication-A Review
(2014-03-01)
Lee, Yao-Jen
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Cho, Ta-Chun
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Chuang, Shang-Shiun
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Hsueh, Fu-Kuo
;
Lu, Yu-Lun
Microwave annealing (MWA) and rapid thermal annealing (RTA) of dopants in implanted Si are compared in their abilities to produce very shallow and highly activated junctions. First, arsenic (As), phosphorus (P), and BF2 implants in Si substrate were annealed by MWA at temperatures below 550 degrees C. Next, enhancing the substitutional carbon concentration ([C] sub) by cluster carbon implantation in (100) Si substrates with MWA or RTA techniques was investigated. Annealing temperatures and time effects were studied. Different formation mechanisms of SiCx layer were observed. In addition, substrate temperature is an important factor for dopant activation during MWA and in situ doped a-Si on oxide/Si substrate or glass were compared to elucidate the substrate temperature effect. After the discussion of dopant activation in Si substrates, low temperature formation of ultrathin NiGe layer is presented. Ultrathin NiGe films with low sheet resistance have been demonstrated with a novel two-step MWA process. In the two-step MWA process, the first step anneals the sample with low power MWA, and the second step applies higher power MWA for reducing sheet resistance. During fixed-frequency microwave heating, standing wave patterns may be present in the MWA chamber resulting in nodes and antinodes and thermal variations over the process wafer. Therefore, the effects of Si or quartz susceptor wafers on dopant activation and sheet resistance uniformity during fixed-frequency MWA were investigated.
Monolithic 3D Chip Integrated with 500ns NVM, 3ps Logic Circuits and SRAM
(2013)
Shen, Chang-Hong
;
Shieh, Jia-Min
;
Wu, Tsung-Ta
;
Huang, Wen-Hsien
;
Yang, Chih-Chao
For the first time, a sequentially processed sub-50nm monolithic 3D IC with integrated logic/NVM circuits and SRAM is demonstrated using multiple layers of ultrathin-body (UTB) MOSFET-based circuits interconnected through 300nm-thick interlayer dielectric (ILD). High-performance sub-50nm UTB MOSFETs using deposited ultra-flat and ultra-thin (20nm) epi-like Si enable across-layer and in-layer high-speed 3ps logic circuits and 1-T 500ns plasma-MONOS NVMs as well as 6T SRAMs with static noise margin (SNM) of 280 mV and reduced footprint by 25%. Closely stacked monolithic 3D circuits envision advanced high-performance, rich function, and low power intelligent mobile devices.