Browsing by Author "Yang, Wen-Luh"

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A highly reliable multi-level and 2-bit/cell operation of wrapped-select-gate (WSG) SONOS memory with optimized ONO thickness
(2007)
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Peng, Wu-Chin
;
Yang, Wen-Luh
;
Wang, Jer-Chyi
High-performance wrapped-select-gate (WSG) SONOS (silicon-oxide-nitride-silicon) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism with different ONO thickness in WSG-SONOS memory was well investigated. The different programming efficiency of the WSG-SONOS memory with different ONO thickness can be explained by the lateral electrical field extracted from the simulation. Furthermore, multi-level storage is easily obtained and well V-th distribution is also presented. High program/erase speed (10us/5ms) and low programming current (3.5uA) are performed to achieve the multi-level operation with excellent gate and drain disturbance, second-bit effect, data retention and endurance.
A Novel Ion-Bombarded and Plasma-Passivated Charge Storage Layer for SONOS-Type Nonvolatile Memory
(2012-10-01)
Liu, Sheng-Hsien
;
Yang, Wen-Luh
;
Wu, Chi-Chang
;
Chao, Tien-Sheng
;
電子物理學系
A novel technique combination of ion bombardment (IB) and NH3 plasma treatment (PT) has been presented to yield a highly effective charge storage layer for Si/SiO2/Si3N4/SiO2/Si (SONOS)-type nonvolatile memory applications. The IB technique creates additional trap sites within the charge storage layer strikingly to enhance the charge trapping/detrapping efficiency of the storage layer, and the NH3 PT passivates shallow trap sites significantly to improve reliability characteristics. The distribution of trap sites corresponding with various energy levels is clearly described by discharge-based multipulse analysis. As compared with the control sample (without IB and NH3 PT), the ion-bombarded and NH3-plasma-passivatedmemory device has faster program/erase speeds and larger memory window. In addition, the competent reliability properties of the ion-bombarded and NH3-plasma-passivated memory, such as good endurance, long data retention, and acceptable disturbance, were also demonstrated in this letter.
A Robust Data Retention Characteristic of Sol-Gel-Derived Nanocrystal Memory by Hot-Hole Trapping
(2010-07-01)
Wu, Chi-Chang
;
Ko, Fu-Hsiang
;
Yang, Wen-Luh
;
You, Hsin-Chiang
;
Liu, Fu-Ken
A new sol-gel-derived Ti(x)Zr(y)Si(z)O nanocrystal (NC) memory with a high-performance data retention characteristic is demonstrated by the hot-hole-trapping method. Prior to rapid thermal annealing, the high-density NC layer is formed by depositing a well-mixed solution of titanium tetrachloride, silicon tetrachloride, and zirconium tetrachloride. The electrical properties of the sol-gel-derived NC memory are demonstrated in terms of memory window, charge retention, program speed, and endurance. The memory window of the NC memory from the novel hot-hole-trapping mechanism can be achieved up to 4.18 +/- 0.21 V, and long retention times obtained from extrapolation up to 10(6) s are observed as 8%, 13%, and 21% window narrowing under respective temperatures of 25 degrees C, 85 degrees C, and 125 degrees C. The good electrical performance is attributed to the contribution of the high density of isolated NCs and hole-trapped into the deep-trap energy level, so no significant lateral and vertical charge leakage occurs.
Advanced Cu chemical displacement technique for SiO2-based electrochemical metallization ReRAM application
(2014-10-28)
Chin, Fun-Tat
;
Lin, Yu-Hsien
;
You, Hsin-Chiang
;
Yang, Wen-Luh
;
Lin, Li-Min
This study investigates an advanced copper (Cu) chemical displacement technique (CDT) with varying the chemical displacement time for fabricating Cu/SiO2-stacked resistive random-access memory (ReRAM). Compared with other Cu deposition methods, this CDT easily controls the interface of the Cu-insulator, the switching layer thickness, and the immunity of the Cu etching process, assisting the 1-transistor-1-ReRAM (1T-1R) structure and system-on-chip integration. The modulated shape of the Cu-SiO2 interface and the thickness of the SiO2 layer obtained by CDT-based Cu deposition on SiO2 were confirmed by scanning electron microscopy and atomic force microscopy. The CDT-fabricated Cu/SiO2-stacked ReRAM exhibited lower operation voltages and more stable data retention characteristics than the control Cu/SiO2-stacked sample. As the Cu CDT processing time increased, the forming and set voltages of the CDT-fabricated Cu/SiO2-stacked ReRAM decreased. Conversely, decreasing the processing time reduced the on-state current and reset voltage while increasing the endurance switching cycle time. Therefore, the switching characteristics were easily modulated by Cu CDT, yielding a high performance electrochemical metallization (ECM)-type ReRAM.
Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals
(2010-08-01)
Chiang, Tsung-Yu
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Wu, Yi-Hong
;
Ma, William Cheng-Yu
;
Kuo, Po-Yi
;
Wang, Kuan-Ti
In this paper, silicon-oxide-nitride-oxide-semiconductor (SONOS) devices with embedded silicon nanocrystals (Si-NCs) in silicon nitride using in situ method with multilevel and 2-b/cell operation have been successfully demonstrated. The proposed in situ Si-NC deposition method exhibits the advantages of low cost, simplicity, and compatibility with modern IC processes. SONOS memories with embedded Si-NCs exhibit a significantly improved performance with a large memory window (> 5.5 V), low operating voltage (P/E voltage: V(g) = 6 V, V(d) = 7 V and V(g) = -7 V, V(d) = 10 V, respectively), greater tolerable gate and drain disturbance (V(t) shift < 0.2 V), negligible second-bit effect, high P/E speed (after programming time = 10 mu s with a 2-V shift of V(t) under V(g) = V(d) = 6 V operation), good retention time (> 10(8) s for 13% charge loss), and excellent endurance performance (after 10(4) P/E cycles with a memory window of 3 V).
Fabrication of SONOS-type flash memory with the binary high-k dielectrics by the sol-gel spin coating method
(2007)
Ko, Fu-Hsiang
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You, Hsin-Chiang
;
Chang, Chun-Ming
;
Yang, Wen-Luh
;
Lei, Tan-Fu
We fabricated the binary high-k (HfxZr1-xO2) nanocrystal memory using a very simple sol-gel spin coating method and 900 degrees C 60 s rapid thermal annealing (RTA). From the transmission electron microscopy identification, the nanocrystals were formed as the monolayered charge trapping site after 900 degrees C 60 s RTA and the size was ca. 5 nm. We verified the electrical properties in terms of program-erase speed, charge retention, and endurance. The sol-gel device exhibited the long charge retention time of 10(4) s with only 2.5% charge loss, and good endurance performance for program/erase cycles up to 10(5). (c) 2007 The Electrochemical Society.
Facile sol-gel preparation of nanocrystal embedded thin film material for memory device
(2013-01-01)
Wu, Chi-Chang
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Tsai, Yi-Jen
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Liu, Pin-Lin
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Yang, Wen-Luh
;
Ko, Fu-Hsiang
A promising charge trapping film with crystal embedded material is proposed for future electronic devices. Instead of conventional high-vacuum and expensive tool, this technique adopts very cheaper process of sol-gel spin-coating for fabrication of thin film material in the charge trapping flash memory (CTFM). The crystal from spinodal phase separation is observed for sol-gel thin film at 900 degrees C annealing, and is strongly related to the thickness of the spin-coated thin film. The morphology of the crystal from the ethanol solvent system is in the isolated form, while from 2-propanol solvent is in the interconnected structure. The sol-gel-derived CTFM from ethanol exhibits the better memory performance of retention times for <5 and <10 % charge loss at applied temperature of 25 and 85 degrees C, respectively. The ethanol system CTFM demonstrates a large memory window (similar to 10 V) and good reliability than 2-propanol (similar to 3 V) due to the existence of several isolated crystals in silicon dioxide film.
High Performance Cu-doped SiO2 ReRAM by a Novel Chemical Soak Method
(2011-01-01)
Chin, Fun-Tat
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Yang, Wen-Luh
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Chao, Tien-Sheng
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Chang, Yuan-Ming
;
Lin, Li-Min
In this paper, a novel chemical soak method is proposed to fabricate a Cu-doped SiO2 ReRAM device. This method can easily fabricate a lightly Cu-doped SiO2 film and effectively improve the reliability of the conventional Cu-doped SiO2 ReRAM device. A reproducible bipolar switching characteristic with set/reset voltage (ca. 2.5 V/ -0.7 V) is performed in this device and the electrical conduction in HRS and LRS are related to Poole-Frenkel and Ohmic conduction, respectively. Excellent performance in terms of high on/off ratio (similar to 10(6)), narrow range distribution of set and reset voltages, stable data retention, and up to 110 times switching cycles has been achieved by this novel chemical soak method for Cu-doped SiO2 ReRAM device.
High-Performance Double-Layer Nickel Nanocrystal Memory by Ion Bombardment Technique
(2013-10-01)
Liu, Sheng-Hsien
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Yang, Wen-Luh
;
Lin, Yu-Hsien
;
Wu, Chi-Chang
;
Chao, Tien-Sheng
A novel ion bombardment (IB) technique is presented to fabricate and embed double-layer (DL) Ni nanocrystal (NC) in silicon nitride for TaN/Al2O3/Si3N4/SiO2/Si nonvolatile memory applications. In contrast to other methods of forming DL metal NC, the IB technique is a relatively simple fabrication method and completely compatible with the current IC manufacturing technologies. Using the IB technique, a high-quality ultrathin interlayer between top and bottom layered NCs can be easily formed and controlled. Compared with the control sample, the IB-induced DL Ni NC memory exhibits superior performance in terms of faster program and erase (P/E) speeds, longer data retention, better endurance, negligible program disturbance, and great potential for a multilevel operation. In addition, the IB-induced DL Ni NC device also shows higher P/E efficiency as well as similar excellent reliability by comparison with other conventional DL metal NC memories due to the high-quality ultrathin interlayer.
High-Performance Polyimide-Based ReRAM for Nonvolatile Memory Application
(2013-01-01)
Liu, Sheng-Hsien
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Yang, Wen-Luh
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Wu, Chi-Chang
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Chao, Tien-Sheng
;
Ye, Meng-Ru
In this letter, high-performance polyimide (PI)-based resistive random access memory (ReRAM) is presented by utilizing a new DAXIN-PI thin film as a resistance layer. The switching between high-and low-resistance states is triggered by the formation and dissociation of the charge transfer complex. As compared with the electrochemical-metallization-based ReRAM and the valence-change-based ReRAM, this DAXIN-PI ReRAM shows excellent performance, including large Ron/Roff ratio, superior endurance, low operation voltage, fast switching speed, needless of a forming process, and acceptable retention characteristics. Among them, large Ron/Roff ratio (> 10(5)) and superior endurance (> 10(5) cycles) can be simultaneously achieved, and the detailed reliability test for PI-based ReRAMs has been analyzed for the first time.
High-program/erase-speed SONOS with in situ silicon nanocrystals
(2008-10-01)
Chiang, Tsung-Yu
;
Chao, Tien-Sheng
;
Wu, Yi-Hong
;
Yang, Wen-Luh
;
電子物理學系
In this letter, for the first time, we have successfully fabricated silicon-oxide-nitride-oxide-silicon (SONOS) devices with embedded silicon nanocrystals (Si-NCs) in silicon nitride using in situ method. This process is simple and compatible to modern IC processes. Different Si-NCs deposition times by in situ method were investigated at first. SONOS devices with embedded Si-NCs in silicon nitride exhibit excellent characteristics in terms of larger memory windows (> 5.5 V), lower operation voltage, high P/E speed, and longer retention time (> 10(8) s for 13% charge loss).
High-Reliability Dynamic-Threshold Source-Side Injection for 2-Bit/Cell With MLC Operation of Wrapped Select-Gate SONOS in NOR-Type Flash Memory
(2010-09-01)
Wang, Kuan-Ti
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Chao, Tien-Sheng
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Wu, Woei-Cherng
;
Yang, Wen-Luh
;
Lee, Chien-Hsing
For the first time, a high-performance (tau(PGM) = 200 ns/tau(ERS) = 5 ms) cell with superior reliability characteristics is demonstrated in a NOR-type architecture, using dynamic-threshold source-side injection (DTSSI) in a wrapped select-gate silicon-oxide-nitride-oxide-silicon memory device, with multilevel and 2-bit/cell operation. Using DTSSI enables easy extraction of the multilevel states with a tight V(TH) distribution, a nearly negligible second-bit effect, superior endurance characteristics, and good data retention.
High-Speed Multilevel Wrapped-Select-Gate SONOS Memory Using a Novel Dynamic Threshold Source-Side-Injection (DTSSI) Programming Method
(2009-06-01)
Wang, Kuan-Ti
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Chao, Tien-Sheng
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Wu, Woei-Cherng
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Chiang, Tsung-Yu
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Wu, Yi-Hong
A. high programming speed with a low-power-consumption wrapped-select-gate poly-Si-oxide-nitride-oxide-silicon memory is successfully demonstrated using the novel dynamic threshold source-side-injection programming technique. The select gate embedded in such particular memory structure acts like a dynamic MOSFET resulting in programming current (I(PGM)) that can be enhanced in this DT mode, easily attaining a high programming speed of about 100 ns. It still doubles the memory density by achieving the 2-bit/cell operation with MLC under DT mode.
Highly reliable multilevel and 2-bit/cell operation of wrapped select gate (WSG) SONOS memory
(2007-03-01)
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Peng, Wu-Chin
;
Yang, Wen-Luh
;
Wang, Jer-Chyi
In this letter, high-performance and reliable wrapped select gate (WSG) polysilicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multilevel and 2-bit/cell operation have been successfully demonstrated. The multilevel storage is easily obtained with fast program/erase speed (10 mu s/5 ms) and low programming current (3.5 mu A) for our WSG SONOS by a source-side injection. Besides the excellent reliability properties of our multilevel WSG-SONOS memory including unconsidered gate and drain disturbance, long charge retention (> 150 degrees C) and good endurance (> 10(4)) are also presented. This novel WSG-SONOS memory with a multilevel and 2-bit/cell operation can be used in future high-density and high-performance memory application.
Improving electrical characteristics of high-k NiTiO dielectric with nitrogen ion implantation.
(2006-09-01)
Yang, Wen-Luh
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Chao, Tien-Sheng
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Chen, Shine-China
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Yang, Chin-Hao
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Peng, Wu-Chin
A new high-dielectric-constant (k) NiTiO dielectric film with a low temperature has been investigated for the first time. The k of the NiTiO film was estimated to be larger than 40. The roughness of the NiTiO dielectric film to nitrogen ion implantation (I/I) was uniform, thus causing a low leakage current (< 10(-9) A) and a high breakdown voltage (> 25 MV/cm(2)). These results are superior to those reported in the literature, suggesting a potential use of the NiTiO film as dielectric for future RF/mixed IC applications.
Ion-Bombarded and Plasma-Passivated Charge Storage Layer for SONOS-Type Nonvolatile Memory
(2014-09-01)
Liu, Sheng-Hsien
;
Wu, Chi-Chang
;
Yang, Wen-Luh
;
Lin, Yu-Hsien
;
Chao, Tien-Sheng
This paper examined the application of ion bombardment (IB) and NH3 plasma treatment (PT) techniques in fabricating a high-performance Si3N4 charge storage layer. The IB technique can be used for creating numerous additional trap sites in the storage layer to enhance charge trapping efficiency and also causes changes in trap centroid location. In addition, the effect of centroid location on operation efficiency and reliability was investigated. Using gate-sensing and channel-sensing analysis, the changes in centroid location were demonstrated. In addition, the energy-level distribution of trap sites was clearly delineated by performing discharge-based multipulse analysis. The NH3 PT technique can substantially passivate IB-induced shallow trap sites to increase data retention time. The influence of the NH3 PT time on the memory characteristics of an IB-induced Si3N4 sample was investigated. The optimal characteristics of an ion-bombarded and plasma-passivated Si3N4 storage layer are presented. Compared with the conventional Si3N4 storage layer, the optimal ion-bombarded and plasma-passivated Si3N4 sample exhibited higher operation efficiency and superior reliability.
Local Strained Channel (LSC) nMOSFETs by different poly-Si gate and SiN capping layer thicknesses: Mobility enhancement, size dependence, and hot carrier stress
(2006)
Lee, Yao-Jen
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Fan, Chia-Hao
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Yang, Wen-Luh
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Lin, Wen-Yan
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Huang, Bohr-Ran
Nanocrystallization and interfacial tension of sol-gel derived memory
(2008-03-24)
Wu, Chi-Chang
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Tsai, Yi-Jen
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Chu, Min-Ching
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Yang, Shao-Ming
;
Ko, Fu-Hsiang
The formation of the nanocrystals (NCs) by using the sol-gel spin-coating method at various annealing temperatures had been studied. The film started to form the islands at 600 degrees C annealing, and finally transferred into NCs at 900 degrees C. A model was proposed to explain the transformation of thin film. The morphology of sol-gel thin film at 600 degrees C annealing was varied and had higher interfacial energy. The crystallized process at 900 degrees C annealing could minimize the energy. The retention for 900 degrees C annealed sample exhibited less than 30% charge loss after 10(6) s at 125 degrees C measurement. (c) 2008 American Institute of Physics.
Novel coexisted sol-gel derived poly-Si-oxide-nitride-oxide-silicon type memory
(2007-11-01)
You, Hsin-Chiang
;
Wu, Chi-Chang
;
Ko, Fu-Hsiang
;
Lei, Tan-Fu
;
Yang, Wen-Luh
The authors use a very simple sol-gel spin coating method at 900 degrees C and 1 min rapid thermal annealing to fabricate three different poly-Si-oxide-nitride-oxide-silicon-type flash memories. The memory windows estimated from the curve of drain current versus applied gate voltage are 3, 3.3, and 4 V for (i) HfO2 thin film, (ii) hafnium silicate nanocrystal, and (iii) coexisted hafnium silicate and zirconium silicate nanocrystal memory, respectively. Together with the measurement from gate disturbance and drain disturbance on these fabricated devices, the coexisted nanocrystal devices exhibit better reliability than both the thin film type memory and single nanocrystal type memory. (C) 2007 American Vacuum Society.
Novel Ion Bombardment Technique for Doping Limited Cu Source in SiOx-Based Nonvolatile Switching Layer
(2013-11-01)
Liu, Sheng-Hsien
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Yang, Wen-Luh
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Lin, Yu-Hsien
;
Wu, Chi-Chang
;
Chao, Tien-Sheng
A novel ion bombardment (IB) technique is presented to dope a limited Cu source in an SiOx switching layer (SiOx:Cu SL) for nonvolatile memory applications. Compared with other Cu-doping methods, this IB technique has many benefits, including a local-doping effect, room-temperature process, and compatibility with current IC manufacturing technology, besteading the 1T-1R integration. Through transmission electron microscopy and energy dispersive spectrometer analyses, an IB-induced SiOx:Cu SL is confirmed. In contrast with the conventional Cu/SiOx-stacked sample, this IB-induced SiOx:Cu SL exhibits superior performance in terms of lower forming/RESET voltages, higher uniformity of SET/RESET voltages, and more stable high-temperature retention characteristics. Additionally, so far, this IB-induced TaN/SiOx:Cu/TaN device has shown the best switching endurance properties for the general SiOx-based Cu filament resistance random access memory.