Browsing by Author "Yang, Yu-Tao"

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A 0.0354mm(2) 82 mu W 125KS/s 3-Axis Readout Circuit for Capacitive MEMS Accelerometer
(2013)
Lai, Kelvin Yi-Tse
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He, Zih-Cheng
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Yang, Yu-Tao
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Chang, Hsie-Chia
;
Lee, Chen-Yi
In this paper, we propose a power/area-efficient capacitive readout circuit for the Micro-Electro-Mechanical Systems (MEMS) sensor of 3-axis accelerometer. The proposed architecture is different from other traditional structures by exploiting true capacitive-to-digital converter (CDC) without Analog-to-Digital Converter (ADC). The proposed CDC can differentiate the bidirectional 125KS/s 80-level accelerations between +/- 8g and support the 4-level adjustable resolutions of 0.1g/0.2g/0.4g/0.8g for each axis. The proposed readout circuit with 0.0354mm(2) area is fabricated in UMC 0.18um CMOS-MEMS process. Experimental results show power consumption is 50uW with 1.8V supply voltage for 1-axis (FOM=3.84pJ), 82uW for 3-axis (FOM=2.1pJ) under 125KHz of sampling frequency and 0.1g acceleration sensitivity for 0.2fF MEMS capacitance change.
A 3.3V 15.6b 6.1pJ/0.02% RH with 10ms Response Humidity Sensor for Respiratory Monitoring
(2014)
Lai, Kelvin Yi-Tse
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Yang, Yu-Tao
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Chen, Bang-Jing
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Shen, Chun-Jen
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Shiu, Ming-Feng
An event-driven and energy-efficient humidity sensor for environment detection and healthcare monitoring is presented. A differential CMOS-MEMS humidity device and proportion-based capacitance-to-digit readout circuit are proposed to overcome PVT variations, and in the meantime to improve sensitivity, response time, and conversion energy. This chip achieves 15.6b 20-90 % RH at 1KS/s, 6.1pJ per 0.02% RH of sensitivity, and 10ms fast response time in TSMC 0.35-mu m CMOS MEMS process. With variations in temperature and voltage, our proposal can minimize the errors from 40% RH to 0.2% RH and 50% RH to 0.1% RH, making it very suitable for wearable respiratory monitoring.
A DIGITAL MICROFLUIDIC PROCESSOR FOR BIOMEDICAL APPLICATIONS
(2013)
Lai, Kelvin Yi-Tse
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Yang, Yu-Tao
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Wang, Gary
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Lu, Yi-Wen
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Lee, Chen-Yi
A digital microfluidic processor for biomedical detection is presented. This processor integrates the functions of droplet actuation, droplet position/shape/volume detection and capacitive measurement window to demonstrate a novel prototype for personalize medicine. In this proposed system, the location map of microdroplets and reaction behaviors are visible on 2-dimentional (2D) graphical user-interface due to capacitive sensing technology and hence automatic signal processing is achievable. Fabricated in standard 0.35um 2P4M CMOS process, this test chip integrates 900 microelectrodes with measurement window in 3.2mm(2). Measurement results show that operation of microdroplet moving is under 1KHz and digital signal extractions of position detection and statistical analysis are under 1MHz respectively.
A Field-Programmable Lab-on-a-Chip with Built-in Self-Test Circuit and Low-Power Sensor-Fusion Solution in 0.35 mu m Standard CMOS Process
(2015)
Lai, Kelvin Yi-Tse
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Shiu, Ming-Feng
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Lu, Yi-Wen
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Ho, Yingchieh
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Kao, Yu-Chi
This paper presents a field programmable lab-on-a-chip (FPLOC) with microfluidics actuation, droplet location/category readback, built-in-self-test (BIST), and bioassays detection. This FPLOC is composed of 1,800 MEDA microelectrodes and integrates a set of microfluidic operations to perform droplet moving/cutting/mixing. Besides, capacitive sensing circuits are considered for system automation, droplets classification, malfunctioning microelectrodes and surface flatness testing, and biomedical detection. Implemented in 0.35 mu m standard CMOS process in 7.4mm(2), the FPLOC demonstrates microfluidic operations under 25V at 1KHz, 1.3fF resolution for droplet location/category/chip BIST maps readback at 1MHz, and 0.34fF sensitivity of capacitive measurement window for biomedical detection at 1KHz.
Adhesion Property of Polyimide and Passivation Layer for Polymer/metal Wafer-level Hybrid Bonding in 3D Integration
(2018-01-01)
Lu, Cheng-Hsien
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Kho, Yi-Tung
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Yang, Yu-Tao
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Chen, Yu-Pei
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Chen, Chiao-Pei
In this paper, the four-point bending method experiments were carried out with different polyimides and passivation layers for realization of adhesion property below 400 degrees C. Three types of passivation layers, thermal oxide, tetraethoxysilane (TEOS) oxide, silicon nitride, and three types of polyimides, with hydrophobic silane, with hydrophilic silane and without silane, and annealing temperature were all considered in this paper. Moreover, the relation between adhesion strength and surface roughness is discussed. Finally, a low thermal budget (250-375 degrees C) polyimide/metal hybrid bonding scheme with good stress release was proposed for future hybrid bonding applications.
An Advanced 2.5-D Heterogeneous Integration Packaging for High-Density Neural Sensing Microsystem
(2017-04-01)
Hu, Yu-Chen
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Huang, Yu-Chieh
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Huang, Po-Tsang
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Wu, Shang-Lin
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Chang, Hsiao-Chun
In the traditional neural sensing microstructure, the limited metal line pitch and the metal layer numbers restrict the neural signal routing ability from electrodes to circuit chips. Miniature packaging and excessive noise interference bottlenecks are some of the challenges faced by the electrodes and circuit chips integration with traditional wire bonding. This paper proposes a 2.5-D heterogeneous integration neural sensing microsystem based on the silicon substrate to overcome these issues. With standard semiconductor and 3-D integration processes, high-channel-density (256 channels at 25 mm(2)) neural sensing microsystem is achieved. Through silicon via provides the shortest vertical interconnection and dramatically minimizes the packaging. Furthermore, the interposer can carry multiple chips to enhance the function of the biosensor. Electrical characteristics and reliability examinations reveal its high quality and great performance as compared to traditional approaches. This novel highly integrated neural sensing microsystem is expected to contribute to the biomedical field for exploring and solving unknown biological mysteries.
An Advanced 3D/2.5D Integration Packaging Approach Using Double-Self-Assembly Method with Complex Topography, and Micropin-Fin Heat Sink Interposer for Pressure Sensing System
(2016-01-01)
Hu, Yu-Chen
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Lin, Chun-Pin
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Chang, Hsiao-Chun
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Yang, Yu-Tao
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Chen, Chi-Shi
To cater complex topography sensors and circuit chips for smart lifestyle applications using Internet of Things (IoT), we develop a novel efficient double-self-assembly packaging approach by 3D/2.5D heterogeneous integration. This technology is able to integrate various kinds of processed chips, especially with uneven surface and bottom topography. With liquid surface tension, complex topography chips can be handled and self-aligned on precise locations. Double-self-assembly approach demonstrates temporary bonding on carrier wafer and self-aligned permanent bonding in a pressure sensing system packaging. The optimized volume of liquid to use on various complex topography shapes and areas are investigated, while Cu/In low temperature metal bonding and self-assembly approach for high I/O density and low bonding resistance are demonstrated. Excellent electrical characteristics and mechanical strength of show the feasibility of the double-self-assembly approach on complex topography surface chips packaging applications.
An Intelligent Digital Microfluidic Processor for Biomedical Detection
(2015-01-01)
Lai, Kelvin Yi-Tse
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Yang, Yu-Tao
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Lee, Chen-Yi
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
An intelligent digital microfluidic processor for biomedical detection is presented. This potential architecture solves lots of traditional development bottlenecks to implement the easy-to-control, easy-to-monitor, system automation and high accuracy for bioassay detection purposes. The proposed processor integrates the functions of microfluidic actuation, droplet location readback and high sensitivity measurement window to demonstrate a novel prototype for personalized medicine. Furthermore, the droplet location map and reaction behaviors are visible on a 2-dimentional (2D) graphical user-interface due to the micro electrode dot array (MEDA) architecture and capacitive sensing technology, and hence system automation is achievable. Fabricated in standard 0.35 mu m CMOS process, this work integrates 900 microelectrodes with measurement window in 3.2 mm(2), where the high sensitivity capacitive readout circuit occupies only 0.048 mm(2). Measurement results show that microdroplet actuation and 2D location map are activated under 1KHz. In addition, the function of digital signal extraction, processing, as well as statistical analysis can be operated under 1 MHz respectively.
Breakthrough in Cu to Cu Pillar-Concave Bonding on Silicon Substrate with Polymer Layer for Advanced Packaging, 3D, and Heterogeneous Integration
(2017-01-01)
Yang, Yu-Tao
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Yu, Ting-Yang
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Kuo, Shu-Chiao
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Huang, Tai-Yuan
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Yang, Kai-Ming
In this paper, finite element method (FEM) simulations are carried out with pillar-concave structure using silicon substrate, silicon substrate with polyimide (PI) and with polybenzoxazole (PBO) for realization of Cu-Cu bonding at low temperature. Parameters of bonding temperature, pillar diameter, concave sidewall angle, and multilayer of concave structure are all considered in simulation. In addition, pillarconcave bonding is successfully demonstrated on silicon substrates with bonding temperatures ranging from 60 degrees C to 100 degrees C. Simulation and fabrication results of concept show potential impacts on current semiconductor packaging method with advantages such as high adhesive strength of polymer on various types of substrates, simplified manufacturing process, solder free interconnect and packaging process, Cu-Cu direct bonding at temperature lower than 100 degrees C, and high tolerance in surface roughness.
High Transmittance Broadband THz Polarizer Using 3D-IC Technologies
(2017-01-01)
Chi, Nai-Chen
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Yu, Ting-Yang
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Tsai, Hsin-Cheng
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Wang, Shiang-Yu
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Luo, Chih-Wei
A novel method of fabricating high transmittance and broadband terahertz (THz) polarizers is introduced with several advantages. A polarizer with an approximate 100% transmittance is demonstrated with single central frequency of anti-reflection (AR) layers between 0.5 THz and 2 THz. Broadband polarizer, which has a transmission spectrum of over 70% uniformity, is fabricated by bonding two wafers with different AR layers. The bandwidth of broadband THz polarizer exceeds 1 THz. Extinction ratio of the polarizer is about 30 dB depending on the frequency and Cu wire pitch. The high transmittance and broadband THz polarizer can be achieved through deep reactive-ion etching (DRIE) and wafer bonding. This new fabricating method of THz polarizers has advantages of lower cost, no accurate alignment requirement and robust structure. Therefore, this approach can possibly benefit the mass production of THz optical components in THz applications and even more.
Investigation of Pillar-Concave Structure for Low-Temperature Cu-Cu Direct Bonding in 3-D/2.5-D Heterogeneous Integration
(2020-08-01)
Chou, Tzu-Chieh
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Yang, Kai-Ming
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Li, Jian-Chen
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Yu, Ting-Yang
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Yang, Yu-Tao
With the advantage of high surface-roughness tolerance, the pillar-concave Cu-Cu direct bonding without chemical-mechanical planarization (CMP) is investigated in detail, including the mechanism of thermal compensation, analysis of roughness, bonding strength, and bonding reliability. With the special design of Cu bond structure, excellent bonding results can be achieved under low thermal budget (150 degrees C for 1 min, atmosphere) with even high roughness of bonding surface. In addition, the pillar-concave scheme applied to fan-out panel-level package (FOPLP) has been demonstrated, showing the high feasibility of this scheme to realize applications in heterogeneous integration.
Low-Temperature Cu-Cu Direct Bonding Using Pillar-Concave Structure in Advanced 3-D Heterogeneous Integration
(2017-09-01)
Yang, Yu-Tao
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Chou, Tzu-Chieh
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Yu, Ting-Yang
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Chang, Yu-Wei
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Huang, Tai-Yuan
Low-temperature Cu-Cu bonding utilizing pillar and concave on silicon substrate with and without polymer layer is successfully implemented at 200 degrees C under atmospheric pressure. Finite-element method (FEM) simulations on stress and deformation generated during bonding process are also presented in order to discuss their influence on bonding result of several pillar diameters and of concave sidewall angles originating from the manufacturing process. The alteration of parameters in FEM simulations would also be investigated to enhance the bonding outcome. The parameters include the diameter of pillar, the sidewall angle of concave, the shape of the concave opening, the addition of extra polymer layer under Cu concave layer, the bonding temperature, and the pitch of the pillar-concave structure. The implementation of Cu-Cu bonding using pillar-concave structure could have a prospective effect on existing packaging methods in semiconductor industry with benefits of applicability to various sorts of substrates and low bonding temperature.
Reliability Investigation and Mechanism Analysis for a Novel Bonding Method of Flexible Substrate in 3D Integration
(2016-01-01)
Yang, Yu-Tao
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Hu, Yu-Chen
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Chen, Kuan-Neng
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A breakthrough in vertical stacking and bonding method in flexible substrates is developed and presented in this paper. Unlike current ACF and NCP approaches, which are used in most manufacturing industry, our novel stacking method uses only metal thin film as bonding material. Two different bonding material bumps are carried out in our experiment. Both show better electrical and reliability outcomes compared to current methods. Our proposed method can reach ultra-fine pitch, metal bonding without polymer material, simplified manufacturing process, better electrical performance and less reliability issues. It can be considered as a future bendable and flexible substrate stacking approach.
Simulation Analysis of Structure Design for Low Temperature Cu-Cu Direct Bonding in Heterogeneous Integration and Advanced Packaging Systems
(2018-01-01)
Pan, Yu-Ming
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Yang, Yu-Tao
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Chou, Tzu-Chieh
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Yu, Ting-Yang
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Yang, Kai-Ming
In order to realize Cu-Cu bonding at low temperature, Cu pillar-concave structures on silicon substrate and on silicon substrate with another polymer layer, polyimide (PI), are both investigated through simulation. Height of Cu pillar, thickness of upper and lower silicon substrate, and thickness of Cu concave are simulated in this paper. The proposed structure could have great impacts on current semiconductor packaging technology, such as improvement of joint strength, enhancement of adhesive strength between various substrates, a Cu-Cu bonding process lower than 200 degrees C with simplified manufacturing process.
Study on Low Temperature Cu Bonding and Temporary Bond/De-Bond for RDL-First Fan-Out Panel Level Package
(2017-01-01)
Ko, Cheng-Ta
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Yang, Kai-Ming
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Lin, Jim-Wein
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Wang, Chih-Lun
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Chou, Tzu-Chieh
In this study, Cu-Cu bonding with pillar-concave structure on a polymer layer was investigated to realize better bonding quality at lower temperature, while a low-stress release layer for temporary bond and de-bond by laser ablation was demonstrated to handle a glass panel for re-distribution layer (RDL) process. The low temperature technology can be potentially applied for RDL-first fan-out panel level package (FOPLP).
Uneven-Topography-Chip Packing Approach Using Double-Self-Assembly Technology for 3-D Heterogeneous Integration
(2018-02-01)
Shen, Wen-Wei
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Chang, Hsiao-Chun
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Yang, Yu-Tao
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Hu, Yu-Chen
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Chen, Kuan-Neng
Although chip-level heterogeneous integration has high yield for production, low-throughput issue of chip-to-wafer bonding is necessary to be improved. Due to the uneven topography and small chip size, handling issue and alignment accuracy are important factors that impact the difficulty in heterogeneous integration. Self-assembly technology has a high potential to be applied in 3-D heterogeneous integration. By using hydrophobic film to define the stacking area, hydrophilic chips can be assembled to realize alignment process on these areas through wafer surface tension in a very short time. With this concept, double-self-assembly technology is accomplished to resolve both handling and alignment issues for uneven-topography-chip integration. In this paper, different chip sizes of mu-pillar are simulated to investigate the optimal water volume for double-self-assembly process. High alignment accuracy of misalignment measurement can be accomplished with the optimal water volume. Furthermore, microstructure of Cu/In bonded structures and corresponding electrical analyses are evaluated, while various reliability tests are investigated for bonding quality. Excellent results verify that the double-self-assembly technology could be applied to 3-D heterogeneous integration for uneven-topography-chip integration.