Browsing by Author "Yeh, CF"

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A new observation of the germanium outdiffusion effect on the hot carrier and NBTI reliabilities in sub-100nm technology strained-Si/SiGe CMOS devices
(2005)
Chung, SS
;
Liu, YR
;
Yeh, CF
;
Wu, SR
;
Lai, CS
In this paper, the evidence of SiGe layer induced trap generation and its correlation with enhanced degradation in strained-Si/SiGe CMOS devices have been reported for the first time. First, a new two-level charge pumping(CP) curve has been demonstrated to identify the Ge out-diffusion effect. Secondly, enhanced degradation in strained-Si devices has been clarified based on experimental results. Both n- and p-MOSFE's exhibit different extent of HC degradation effect. This is attributed to the difference in their mobility enhancement as well as additional traps coming from the Si/SiGe interface. Finally, temperature dependence of HC and NBTI has been examined for both strained-Si and bulk devices. Sophisticated measurement techniques, charge pumping and gated-diode (GD) measurements, have been employed to understand the generated interface traps. Results show that strained-Si device is less sensitive to the temperature and has a chance for better NBTI reliability if we have a good control of the strained-Si/SiGe interface, such as through low temperature gate oxide process or better S/D junction formation.
A novel four-mask-processed poly-Si TFT fabricated using excimer laser crystallization of an edge-thickened alpha-Si active island
(2004-06-01)
Chen, TF
;
Yeh, CF
;
Liu, CY
;
Lou, JC
;
電子工程學系及電子研究所
A novel four-mask-processed polycrystalline silicon thin-film transistor (poly-Si TFT) is fabricated using 50-pulse KrF excimer laser to crystallize an edge-thickened amorphous silicon (a-Si) active island without any shrinkage. This method introduces a temperature gradient in the island to enlarge grains from the edge, especially when the channel width is narrow. The grain boundaries across the width of the channel suppress the leakage current and the drain-induced barrier lowering. Moreover, the proposed poly-Si TFT with a channel length of L = 2 mum and a channel width of W = 1.2 mum possesses a high field-effect mobility of 260 cm(2)/Vs and an on/off current ratio of 2.31 x 10(8).
A novel lightly doped drain polysilicon thin-film transistor with oxide sidewall spacer formed by one-step selective liquid phase deposition
(1999-08-01)
Shih, PS
;
Chang, CY
;
Chang, TC
;
Huang, TY
;
Peng, DZ
We have proposed and successfully demonstrated a novel process for fabricating lightly doped drain (LDD) polycrystalline silicon thin-film transistors (TFT's), The oxide sidewall spacer in the new process is formed by a simple one-step selective liquid phase deposition (LPD) oxide performed at 23 degrees C, Devices fabricated with the new process exhibit a lower leakage current and a better ON/OFF current ratio than non-LDD control devices. Since the apparatus used for LPD oxide deposition is simple and inexpensive, the new process appears to be quite promising for future high-performance poly-Si TFT fabrication.
A physically-based built-in Spice Poly-Si TFT model for circuit simulation and reliability evaluation
(1996)
Chung, SS
;
Chen, DC
;
Cheng, CT
;
Yeh, CF
;
交大名義發表
A Poly-Si TFT model for circuit simulation in Spice is presented, combined with a device degradation model for the first time to evaluate the circuit reliability. Both I-V and C-V models for the whole device operating regime have been developed. In the I-V model, emphasis has been taken to derive the mobility degradation induced by the grain boundary potantial barrier height and trap density. The small geometry effect, off-state current and the parasitic BJT effect are also considered in the model. Good agreements between modeled and experimental data were achieved. To evaluate the circuit reliability after electrical stress, the device reliability model has also been developed. Finally, simulation a 27-stage ring oscillator has been demonstrated, which shows delay time of about 1 nsec per stage.
Application of plasma immersion ion implantation doping to low-temperature processed poly-Si TFT's
(1998-11-01)
Yeh, CF
;
Chen, TJ
;
Liu, C
;
Shao, JQ
;
Cheung, NW
This work applied, for the first time, plasma immersion ion implantation (PIII) for source/drain doping on low-temperature processed polysilicon thin-film transistors (poly-Si TFT's), Experimental results indicate that PIII doping can provide adequate dopant concentration and junction depth for source/drain. In addition, H-2-diluted phosphorus pill can promote dopant activation more efficiently during RTA at 600 degrees C than with conventional ion implantation (II) technology. The excellent characteristics of PIII doped poly-Si TFT's resemble those of conventional II doped ones.
Application of selective liquid-phase deposition to fabricate contact holes without plasma damage
(1999-06-01)
Yeh, CF
;
Liu, CH
;
Su, JL
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work develops an alternative method, selective liquid-phase deposition (S-LPD), to fabricate contact holes instead of reactive ion etching. In preliminary experiments, deep n(+)/p junction diodes with contact holes prepared by S-LPD exhibit much less reverse current, unity ideality factor, larger forward current, lower contact resistance, and higher thermal stability than those prepared by reactive ion etching. Further superiority of plasma damage-free near-surface regions is also investigated using Schottky and ultrashallow junction diodes. Experimental results indicate that S-LPD can be applied to the submicron contact-hole process. The data after reverse bias temperature stress reveals the satisfactory reliability of S-LPD contact holes. This work demonstrates that the S-LPD technology is a highly promising means of replacing reactive ion etching processes to form submicron contact holes as reliably as those by wet-etching. (C) 1999 The Electrochemical Society. S0013-4651(98)08-119-1. All rights reserved.
Applying selective liquid-phase deposition to create contact holes in plasma damage-free process
(1998)
Yeh, CF
;
Liu, CH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We apply an alternative plasma damage-free process -- the selective liquid-phase deposition (S-LPD), instead of the conventional RIE to form metal/semiconductor contact holes. This paper studies the performance comparison between S-LPD and RIE to form contact hole in n(+)/p junction diode, Schottky diode, and ohmic contact. In our experiments, if the plasma-free S-LPD technique is adopted, there is excelled performance including lower reverse current, lower ideality factor, higher forward current, high Schottky barrier, lower contact resistance and better thermal stability in these devices.
Approach to room temperature process - A novel thin liquid-phase deposited oxide
(1996)
Yeh, CF
;
Lin, SS
;
交大名義發表
;
電子工程學系及電子研究所
;
National Chiao Tung University
To continuously reduce dimensions, and increase reliability of devices, low-temperature process (LTP) is an important issue. Pursuing a novel LTP, room-temperature process can be as a norm. In this paper, as an approach to room-temperature process, the feasible technologies of versatile liquid-phase deposited oxide will be introduced.
Characteristics of novel polysilicon oxide by anodic oxidation
(1999-09-01)
Yeh, CF
;
Liu, JS
;
Chiang, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
For nonvolatile memory applications, a novel oxide grown on polysilicon by anodic oxidation (anodic polyoxide) is first investigated. In this work, the electrical characteristics of anodic polyoxide is discussed and compared with the conventional thermal polyoxide. The results show that the anodic polyoxide exhibits considerably excellent characteristics, i.e., low leakage current, high breakdown electric field, and high reliabilities.
Characterization and reliability of lightly-doped-drain polysilicon thin-film transistors with oxide sidewall spacer formed by one-step selective liquid phase deposition
(2000-10-01)
Shih, PS
;
Chang, TC
;
Huang, TY
;
Yeh, CF
;
Chang, CY
We have proposed and successfully demonstrated a novel process for fabricating a lightly doped drain (LDD) polysilicon thin-film transistor (poly-Si TFT). The oxide sidewall spacer in the new process is formed by a simple one-step selective liquid phase deposition (LPD) at 23 degreesC. In contrast with conventional methods, this new process does not require an additional photolithographic step for defining the non-self-aligned offset gate, or the deposition of an oxide layer and subsequent etch-back to form the: self-aligned sidewall spacer. Devices fabricated by the new process have a lower leakage current and a better ON/OFF current ratio, compared with non-LDD control devices. The new device also shows excellent current saturation characteristics at high bias and better has hot-carrier endurance. Since the apparatus used for LPD oxide deposition is simple and inexpensive, the new process appears to be promising for future high-performance poly-Si TFT fabrication.
Chemical mechanical polishing of PSG and BPSG dielectric films: The effect of phosphorus and boron concentration
(1995-12-01)
Liu, CW
;
Dai, BT
;
Yeh, CF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Chemical-mechanical polishing of blanket and patterned oxide films doped with phosphorus and boron has been studied. FTIR was used to characterize the film microstructure. Experimental results show that an increase of phosphorus level promoted the polish rate of PSG film. We also found that increasing the boron content enhanced the polish rate of BPSG films although phosphorus contents is decreased. This implies that boron is more effective than phosphorus in enhancing the polishing rate of BPSG films. However, the hardness of these doped films is slightly affected by doping level. Excellent planarity achieved by CMP is demonstrated for patterned wafers. Here, we also identify inversion patterns for the composite dielectric formed by a thin hard film on the top of a thick soft film. Such inversion phenomenon can be used for monitoring CMP process as a means of end point detection.
Comprehensive investigation on fluorosilicate glass prepared by temperature-difference-based liquid-phase deposition
(2000-01-01)
Yeh, CF
;
Lee, YC
;
Wu, KH
;
Su, YC
;
Lee, SC
This study investigates the properties of fluorosilicate glass film prepared by temperature-difference-based liquid-phase deposition. Experimental results indicate that the deposition temperature can significantly affect the deposition rate and film properties. As the deposition temperature increases from 15 to 35 degrees C, the deposition rate increases exponentially from 30 to 687 Angstrom/h. Meanwhile, the F and OH contents increase from 2.56 to 3.49% and from 0.16 to 0.5%, respectively. The dielectric constants;ind stresses for the films deposited at 15, 25, and 35 degrees C, are 3.56/63 MPa, 3.46/43 MPa, and 3.66/73 MPa, respectively. The current densities at 2 MV/cm for the films deposited at 15, 25, and 35 degrees C are 6.9 x 10(-9), 4.6 x 10(-9), and 3.6 x 10(-7) A/cm(2), respectively. For the film deposited at 25 degrees C. the dielectric constant and the stress are minimal because of the high F content, low OH content, and low bond strain. The properties are also compared with those of fluorosilicate glass prepared by plasma-enhanced chemical vapor deposition. In addition to exhibiting a lower dielectric constant and much better resistance to moisture, the film prepared by temperature-difference-based liquid-phase deposition also shows a comparable or better insulating property, revealing a reliable intermetal dielectric with a low dielectric constant. (C) 2000 The Electrochemical Society. S0013-4651(99)04-019-7. All rights reserved.
Device transfer technology by backside etching (DTBE) for poly-Si thin-film transistors on glass/plastic substrate
(2003-09-15)
Wang, SC
;
Yeh, CF
;
Huang, CK
;
Dai, YT
;
電子工程學系及電子研究所
This work presents a novel method entitled "device transfer by backside etching (DTBE)" for transferring thin-film devices from Si wafers to a glass or plastic substrate. First, high performance poly-Si thin-film transistors (TFTs) were fabricated on a Si wafer and then adhered to glass or plastic substrates. The remaining Si was removed delicately using wafer. backside chemical-mechanical polishing (CMP) and wet chemical etching. The devices after transferring exhibit comparable electrical characteristics to the original ones on Si substrates. The new transfer scheme has quite attractive applications for fabricating high-quality displays on low-cost substrates with low melting temperatures.
Effect of processing temperature on polysilicon thin-film transistors with liquid-phase deposited oxide as gate insulator
(1997)
Yeh, CF
;
Chen, TJ
;
Jeng, JN
;
交大名義發表
;
電子工程學系及電子研究所
Liquid-phase deposited (LPD) oxide has been successfully applied as gate insulator to low-temperature processed polysilicon thin-film transistors (poly-Si TFTs). This paper assesses the feasibility of applying LPD oxide to high-temperature processed (HTP) TFTs. The high-temperature treatments like gate-oxide annealing and dopant activation provide excellent improvement in the characteristics of poly-Si TFTs with LPD gate oxides. These high-temperature treated devices show effective hydrogenation using the NH3 plasma treatment. The results imply that novel LPD gate oxide technologies can lead to replacement of thermal gate oxide with HTP poly Si TFTs. The reliability of HTP poly-Si TFTs with LPD gate oxides was also investigated.
Effects of grain boundaries on performance and hot-carrier reliability of excimer-laser annealed polycrystalline silicon thin film transistors
(2004-05-15)
Chen, TF
;
Yeh, CF
;
Lou, JC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work examines the effects of grain boundaries on the performance and hot-carrier reliability of excimer-laser-annealed polycrystalline silicon thin film transistors (poly-Si TFTs) before and after NH3 plasma treatment. Self-aligned poly-Si TFTs, whose channel regions include a 150 nm thick laser-crystallized poly-Si layer with small grains and a 100 nm thick layer with large grains, are fabricated. Other TFTs, with large grains throughout their channels, are fabricated nearby for comparison. The trapping of electrons at grain boundaries in the drain junction creates strong local electric fields that boost the leakage current, cause the threshold voltage to decline as the drain bias increases, enhance the kink effect in the output characteristics, and degrade the hot-carrier reliability of devices. When static hot-carrier stress is applied to nonhydrogenated poly-Si TFTs for less than 10(4) s at V-GS=10 V and V-DS=20 V, hot holes are injected into the gate oxide at the same time trap states are created in the drain junction. The screening effect is observed when the same stress is applied to devices that have many grain boundaries in their drain junctions. NH3 plasma treatment prevents the trapping of electrons at grain boundaries. The performance of hydrogenated poly-Si TFTs improves, but the hot-carrier reliability of those TFTs with large grains in their drain junctions degrades. The hydrogenation causes a trade-off between the electrical characteristics and the hot-carrier reliability, and introduces irregular humps in the subthreshold region. (C) 2004 American Institute of Physics.
Effects of mechanical characteristics on the chemical-mechanical polishing of dielectric thin films
(1996-12-15)
Tseng, WT
;
Liu, CW
;
Dai, BT
;
Yeh, CF
;
電子工程學系及電子研究所
The effects of as-deposited (intrinsic) stress, externally applied (extrinsic) stresses, hardness, and modulus of various dielectric firms on chemical-mechanical polishing (CMP) removal and post-CMP cleaning processes are studied in this article. Intrinsic stresses of the polished dielectrics do not contribute directly to the CMP removal rate. Extrinsic stresses including normal and shear components are calculated using principles of elasticity and fluid mechanics respectively and their roles in the material removal process are discussed. Theoretical evaluation and experimental results both suggest that hardness and modulus are the two most important material characteristics affecting the CMP process. Efficiency of post-CMP particle extraction can be monitored using an adhesion probability which is related to the hardness of wafer and pad. Tn addition, particle removal rate can be remarkably enhanced by increasing pressure (normal stress) while increasing pad rotation speed (shear stress) contributes little to reduce the particle count.
Effects of process temperature on polysilicon thin film transistors with liquid-phase deposited oxides as gate insulators
(1997-10-01)
Yeh, CF
;
Chen, TJ
;
Jeng, JN
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Liquid-phase deposited (LPD) oxide has previously been successfully applied to low temperature processed polysilicon thin film transistors (poly-Si TFTs) as a gate insulator. This paper shows the feasibility of applying room temperature deposited LPD oxide to high temperature processed devices. The thermal effects of high temperature processing on poly-Si TFTs including postoxide annealing and dopant activation have been investigated. These high temperature treatments show excellent improvement in device characteristics. In addition, the novel devices also show considerably more efficient hydrogenation during NH3-plasma treatment, and their reliability under de electrical stress appears similar to that of conventional poly-Si TFTs.
Fabricating thin-film transistors on plastic substrates using spin etching and device transfer
(2005)
Wang, SC
;
Yeh, CF
;
Hsu, CT
;
Lou, JC
;
電子工程學系及電子研究所
This work presents a novel method for transferring thin-film transistors (TFTs) from a Si wafer to another flexible plastic substrate. First, high-performance poly-Si TFTs were fabricated on a 1.5 mu m thick SiO2 on a Si wafer and then attached to a flexible plastic substrate by optical adhesive. Next, spin-etching was utilized to remove the backside Si, using SiO2 as a stopping layer. A qualitative model was established to explain the relationship between the chemical flow rate/rotation speed to the etching rate and the uniformity of Si removal. The Si etching rate exceeded 200 mu m/min while the Si to SiO2 selectivity of 250 was maintained given optimized spin-etching parameters. Substrate bonding and Si spin-etching steps caused no degradation or yield loss as compared to the electrical characteristics before transference. Additionally, extrinsic stress only weakly affected the properties of poly-Si resistors and TF`Ts on a flexible plastic substrate. (c) 2005 The Electrochemical Society. [DOI: 10. 1149/1.1860491] All rights reserved.
Fabrication of thin-film transistors on plastic substrates by spin etching and device transfer process
(2004)
Wang, SC
;
Hsu, CT
;
Yeh, CF
;
Lou, JC
;
電子工程學系及電子研究所
This work presents a novel method to transfer thin-film transistors from a Si wafer to another flexible plastic substrate. First, high-performance poly-Si TFTs were fabricated on 1-mum thick SiO2 of a Si wafer and then adhered to a flexible plastic substrate by the optical adhesive. Next, the spin-etching process was utilized to remove the backside Si with SiO2 as a stopping layer. We have established a qualitative model to explain the relation between the chemical flow rate/rotation speed to the etching rate and the uniformity of Si removal. The Si etching rate is higher than 200 mum/min while maintaining Si to SiO2 selectivity of 250 under optimized spin-etching parameters. Compared to that before transference, no degradation or yield loss was found due to substrate bonding and Si spin-etching steps. Additionally, extrinsic stress shows little effect to the properties of poly-Si resistors on the flexible plastic substrate.
Highly reliable liquid-phase deposited SiO2 with nitrous oxide plasma post-treatment for low temperature processed poly-Si TFT's
(1998)
Yeh, CF
;
Chen, DC
;
Lu, CY
;
Liu, C
;
Lee, ST
Low temperature (similar to 300 degrees C) N2O plasma annealing for liquid-phase deposited (LPD) gate oxide has been proposed for the first time. Physicochemical and electrical characterizations show that the N2O-treated LPD-SiO2 improves breakdown field, interface state density, and Si-rich phenomenon. This novel technology has been also successfully applied to LTP poly-Si TFT's, which reveal excellent characteristics and reliability. It is believed that the N2O plasma post-treatment not only improves the oxide quality, but also passivates the trap states in poly-Si channel.