Browsing by Author "Yeh, Chih-Ting"

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A New Three-Dimensional Capacitor Model for Accurate Simulation of Parasitic Capacitances in Nanoscale MOSFETs
(2009-08-01)
Guo, Jyh-Chyurn
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Yeh, Chih-Ting
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new 3-D gate capacitor model is developed to accurately calculate the parasitic capacitances of nanoscale CMOS devices. The dependences on gate length and width, gate electrode and dielectric thicknesses, gate-to-contact spacing, and contact dimension and geometry are fully incorporated in this model. The accuracy is certified by an excellent match with the 3-D interconnection simulation results for three structures with strip, square, and circular contacts. The features of being free from fitting parameters and proven accuracy over various geometries make this model useful for nanoscale MOSFET parasitic capacitance simulation and analysis. Furthermore, the developed capacitor model in the form of multidimensional integral can easily be deployed in general circuit simulators. This model predicts that the parasitic capacitance C(of) dominates around 25% of the intrinsic gate capacitance (C(gint)) in 80-nm MOSFETs and that the near nonscalability with gate length brings the weighting factor C(of)/C(gint) above 30%/40%/60% in 65-/45-/32-nm devices. It actually exceeds the limitation defined by the most updated ITRS and reveals itself as a show-stopper in high-speed and high-frequency circuit design.
A NOVEL LIQUID-PACKAGING TECHNOLOGY FOR HIGHLY RELIABLE UV-LED ENCAPSULATION
(2019-01-01)
Zhang, Wen-Hua
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Lin, Wei-Keng
;
Yeh, Chih-Ting
;
Chiang, Song-Bor
;
Jao, Chih-Sheng
This paper proposes a liquid-packaging technology for UV LED. Unlike the traditional packaging methods that involve thermosetting silicon or quartz glass, the proposed method primarily uses silicon oil to directly contact the chip, which prevents erosion due to moisture or oxygen. In this study, UV LEDs with high heat dissipation technology were selected, and the experimental results of optical and thermal management were compared between the general packaging and liquid-packaging structures, respectively. The results of the optical experiments showed that the proposed method increases the extraction efficiency by 9.5%. The results of the heat dissipation experiments showed that the liquid-packaging technology can reduce the thermal resistance of the UV-LED package by 31%.
A novel oxidized composite braided wires wick structure applicable for ultra-thin flattened heat pipes
(2017-11-01)
Yang, Kai-Shing
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Tu, Cheng-Wei
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Zhang, Wen-Hua
;
Yeh, Chih-Ting
;
Wang, Chi-Chuan
This present study proposed a novel low-cost and high performance braided wire wick structure having superhydrophilic treatment applicable for ultra-thin heat pipe. The test wick structures include mono and composite wick structure. The composite braided wire adopts two different diameter wire design, using a large diameter (0.1 mm) in the core while the exterior of the core is covered by smaller diameter copper wire (0.05 mm). The mono design contains only one uniform wire diameter (0.1 mm) in core region. Test results indicate that via oxidizing the surface of the braided wires can largely enhance the surface roughness and result in a much higher capillary force as comparing to the un-oxidized one. In addition, both mono (m-FHP) and composite braided wire (c-FHP) with oxidization could possess a maximum heat transfer capability over 15 W under horizontal operation, and test results showed that the heat transfer capability of composite design outperforms mono one by more than 32.5% in all orientations. It is also found that the filling loading ratio plays essential role on the overall performance of FHP. Either a low filling loading ratio or a high filling loading ratio may yield a lower maximum heat transfer capability and a higher thermal resistance. An optimum filling loading ratio of 125% yields the lowest thermal resistance around 0.12 K/W with the best heat transfer capability of 20W.
An experimental and analytical investigation of the photo-thermal-electro characteristics of a high power InGaN LED module
(2016-04-05)
Yang, Kai-Shing
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Ding, Wei-Ting
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Yeh, Chih-Ting
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Lee, Ming-Tsang
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Wang, Chi-Chuan
The photo-thermal-electro characteristics of a high power InGaN LED module were studied both experimentally and theoretically. Three types of heat sink substrate composed of two layers of materials were used to investigate the coupled relationships between chip temperature, thermal resistance, input electric power and light emission efficiency. The results showed that the thermal spreading resistance accounts for a significant fraction of the total substrate thermal resistance. The measured thermal resistance of the LED module increased with rising electric power input. Luminescent efficacy measurements revealed that this increase of thermal resistance was the result of increased heat dissipation from the chip due to less efficient conversion of electric power to light output. Furthermore, experimental results showed that the radiant efficiency of the LED decreases with increasing input electric power. The coupled effects of chip temperature, input power and thermal resistance of the substrate are responsible for this efficiency droop. A revised model for estimating the luminous efficacy that takes both thermal and electrical effects into consideration is proposed. It is shown that the efficiency droop of the LED module for all three types of substrates can be clearly demonstrated by using the proposed analysis. (C) 2015 Elsevier Ltd. All rights reserved.
Area-Efficient Power-Rail ESD Clamp Circuit with SCR Device Embedded into ESD-Transient Detection Circuit in a 65nm CMOS Process
(2013)
Yeh, Chih-Ting
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An area-efficient power-rail electrostatic discharge (ESD) clamp circuit with silicon-controlled rectifier (SCR) as main ESD clamp device has been proposed and verified in a 65nm CMOS process. By modifying the layout structure, the ESD-transient detection circuit can be totally embedded in the SCR device. From the measured results, the proposed power-rail ESD clamp circuit with SCR width of 45 mu m can achieve 7kV human-body-model (HBM) and 350V machinemodel (MM) ESD levels under the ESD stress event, while consuming the standby leakage current in the order of nanoampere at room temperature under the normal circuit operating condition with 1V bias.
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection
(2010-11-01)
Yeh, Chih-Ting
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The RC-based power-rail ESD clamp circuit with the n-channel metal-oxide-semiconductor (NMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been utilized to effectively enhance the ESD robustness of CMOS ICs. In this work, a new ESD-transient detection circuit without using the capacitor has been proposed and verified in a 65 nm 1.2 V CMOS process. The layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%, as compared to the traditional RC-based ESD-transient detection circuit realized with capacitor. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long enough turn-on duration under the ESD stress condition, as well as better immunity against mistrigger and transient-induced latch-on event under the fast power-on and transient noise conditions.
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection
(2010-11-01)
Yeh, Chih-Ting
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
The RC-based power-rail ESD clamp circuit with the n-channel metal-oxide-semiconductor (NMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been utilized to effectively enhance the ESD robustness of CMOS ICs. In this work, a new ESD-transient detection circuit without using the capacitor has been proposed and verified in a 65 nm 1.2 V CMOS process. The layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%, as compared to the traditional RC-based ESD-transient detection circuit realized with capacitor. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long enough turn-on duration under the ESD stress condition, as well as better immunity against mistrigger and transient-induced latch-on event under the fast power-on and transient noise conditions.
Design of Power-Rail ESD Clamp Circuit with Adjustable Holding Voltage against Mis-trigger or Transient-Induced Latch-On Events
(2011)
Yeh, Chih-Ting
;
Liang, Yung-Chih
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work, a new design of the ESD-transient detection circuit with the n-channel metal-oxide-semiconductor (nMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been proposed and verified in a 65nm 1.2V CMOS process. As compared to the traditional RC-based ESD-transient detection circuit, the layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long turn-on duration under the ESD stress condition, as well as better immunity against mis-trigger or transient-induced latch-on event under the fast power-on and transient noise conditions.
High Area-Efficient ESD Clamp Circuit With Equivalent RC-Based Detection Mechanism in a 65-nm CMOS Process
(2013-03-01)
Yeh, Chih-Ting
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A power-rail electrostatic discharge (ESD) clamp circuit realized with ESD clamp device drawn in the layout style of big field-effect transistor (BigFET), and with parasitic diode of BigFET as a part of ESD-transient detection mechanism, is proposed and verified in a 65-nm 1.2-V CMOS process. Skillfully utilizing the diode-connected MOS transistor as the equivalent large resistor and the parasitic reverse-biased diodes of BigFET as the equivalent capacitors, the new RC-based ESD-transient detection mechanism can be achieved without using an actual resistor and capacitor to significantly reduce the layout area by similar to 82%, as compared to the traditional RC-based ESD-transient detection circuit. From the measured results, the new proposed power-rail ESD clamp circuit with body effect of ESD clamp device can perform adjustable holding voltage under the ESD stress condition, as well as better immunity against mistrigger and transient-induced latch-on under fast power-on and transient noise conditions.
Layout Optimization on ESD Diodes for Giga-Hz RF and High-Speed I/O Circuits
(2010)
Yeh, Chih-Ting
;
Liang, Yung-Chih
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The diode operated in forward-biased condition has been widely used as an effective on-chip ESD protection device at GHz RF and high-speed I/O pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes realized in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The new ESD protection diodes can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the waffle diode. Therefore, the signal degradation of GHz RF and high-speed transmission can be reduced due to smaller parasitic capacitance from the new proposed diodes.
Luminescence material characterizations on laser-phosphor lighting techniques
(2019-03-04)
Yeh, Chih-Ting
;
Chou, Yen-, I
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Yang, Kai-Shing
;
Wu, Shih-Kuo
;
Wang, Chi-Chuang
This study examines three different types of laser carriers, including the phosphors in silicone (PiS), the phosphor in glass (PiG), and alumina-based ceramic binders (CP), for laser-phosphor lighting characterizations via a laser projector light source module. The thermal influence of heat spreading on these phosphor materials and their luminescence performance is also investigated. The conversion efficiency of PiS, PiG and CP was found to be 29.7%, 34.6% and 31.8%, with their corresponding maximum laser power operations of 3.9 W, 7.9 W, and 17.2 W, respectively. This work further correlates the maximum laser operation power with the thermal conductivity of luminescence material. From the optical engine perspective, it was found that CP exhibits the superior thermal conductivity of 17.0 W/m.K for slight hot-spot IR observation and higher laser power operation. This work finally delivers a CP device for 50.2W maximum laser operation with the operating temperature below 100 degrees C. The simulation is also carried out in order to examine spreading resistance's influence, when subject to convective boundary condition. CP's response sensitivity to heat transfer coefficient was found to be rather small. (C) 2019 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology
(2012-03-01)
Yeh, Chih-Ting
;
Ker, Ming-Dou
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new 2 x VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit realized with only thin gate oxide 1-V (1 x VDD) devices and a silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. This new design has a low standby leakage current by reducing the voltage difference across the gate oxide of the devices in the ESD detection circuit. The proposed design with an SCR width of 50 mu m can achieve a 6.5-kV human-body-model ESD level, a 300-V machine-model ESD level, and a low standby leakage current of only 103.7 nA at room temperature under the normal circuit operating condition with 1.8 V bias.
On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology
(2014-03-01)
Ker, Ming-Dou
;
Yeh, Chih-Ting
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
CMOS technology has been widely used to produce many integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously increases the difficulty of electrostatic discharge (ESD) protection design. The power-rail ESD clamp circuit has been the key circuit to perform the whole-chip ESD protection scheme. Some ESD detection circuits were developed to trigger on ESD devices across the power rails to quickly discharge ESD current away from the internal circuits. Therefore, on-chip ESD protection circuits must be designed with the consideration of standby leakage to minimize the power consumption and the possibility of malfunction to normal circuit operation. The design of power-rail ESD clamp circuits with low standby leakage current and high efficiency of layout area in nanoscale CMOS technology is reviewed in this paper. The comparisons among those power-rail ESD clamp circuits are also discussed.
Optimization on Layout Style of ESD Protection Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits
(2010-06-01)
Yeh, Chih-Ting
;
Ker, Ming-Dou
;
Liang, Yung-Chih
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The diode operated in forward-biased condition has been widely used as an effective on-chip electrostatic discharge (ESD) protection device at radio-frequency (RF) front-end and high-speed input/output (I/O) pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes drawn in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The measured results confirmed that they can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the stripe and waffle diodes, especially for the diodes drawn in the hollow layout style. Therefore, the signal degradation of RF and high-speed transmission can be reduced because of smaller parasitic capacitance from the new proposed diodes.
PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit
(2013-02-01)
Yeh, Chih-Ting
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new power-rail ESD clamp circuit designed with PMOS as main ESD clamp device has been proposed and verified in a 65 nm 1.2 V CMOS process. The new proposed design with adjustable holding voltage controlled by the ESD detection circuit has better immunity against mis-trigger or transient-induced latch-on event. The layout area and the standby leakage current of this new proposed design are much superior to that of traditional RC-based power-rail ESD clamp circuit with NMOS as main ESD clamp device. (C) 2012 Elsevier Ltd. All rights reserved.
Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology
(2012-10-01)
Yeh, Chih-Ting
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An ultralow-leakage power-rail electrostatic discharge (ESD) clamp circuit realized with only thin gate oxide devices and with silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. By reducing the voltage difference across the gate oxide of the devices in the ESD detection circuit, the proposed power-rail ESD clamp circuit can achieve an ultralow standby leakage current. In addition, the ESD-transient detection circuit can be totally embedded in the SCR device bymodifying the layout structure. From the measured results, the proposed power-rail ESD clamp circuit with an SCR width of 45 mu m can achieve 7-kV human-body-model and 350-V machine-model ESD levels under the ESD stress event while consuming only a standby leakage current in the order of nanoamperes at room temperature under the normal circuit operating condition with 1-V bias.
Resistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology
(2012-12-01)
Yeh, Chih-Ting
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A resistor-less power-rail electrostatic discharge (ESD) clamp circuit realized with only thin-gate-oxide devices and with a silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. By skillfully utilizing the gate leakage current to realize the equivalent resistor in the ESD-transient detection circuit, the RC-based ESD detection mechanism can be achieved without using an actual resistor to significantly reduce the layout area in I/O cells. From the measured results, the new proposed power-rail ESD clamp circuit with an SCR width of 45 mu m can achieve 5-kV human-body-model and 400-V machine-model ESD levels under the ESD stress event while consuming only a standby leakage current of 1.43 nA at room temperature under the normal circuit operating condition with 1-V bias.
Resistor-Less Power-Rail ESD Clamp Circuit with Ultra-Low Leakage Current in 65nm CMOS Process
(2013)
Yeh, Chih-Ting
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A resistor-less power-rail ESD clamp circuit realized with only thin gate oxide devices, and with SCR as main ESD clamp device, has been proposed and verified in a 65nm 1V CMOS process. Skillfully utilizing the gate leakage currents to realize the equivalent resistors in the ESD-transient detection circuit, the RC-based ESD-transient detection mechanism can be achieved without using an actual resistor to reduce the layout area in I/O cells. From the measured results, the proposed power-rail ESD clamp circuit with SCR width of 45 mu m can achieve 5kV HBM and 400V MM ESD levels under the ESD stress event, while consuming only a standby leakage current of 1.43nA at 25 degrees C under the normal circuit operating condition with 1V bias.
Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications
(2012-06-01)
Yeh, Chih-Ting
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
To meet the desired electrostatic discharge (ESD) robustness, ESD diodes was added into the I/O cells of integrated circuits (ICs). However, the parasitic capacitance from the ESD diodes often caused degradation on circuit performance, especially in the high-speed I/O applications. In this work, two modified layout styles to effectively improve the figures of merits (FOMs) of ESD protection diodes have been proposed, which are called as multi-waffle and multi-waffle-hollow layout styles. Experimental results in a 90-nm CMOS process have confirmed that the FOMs (R-ON * C-ESD, I-CP/C-ESD,C- V-HBM/C-ESD, and I-CP/A(Layout)) of ESD protection diodes with new proposed layout styles can be successfully improved. (C) 2011 Elsevier Ltd. All rights reserved.