Browsing by Author "Yeh, Kuo-Liang"

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A New Compact Model for Accurate Simulation of RF Noise in Sub-40nm Multi-finger nMOSFETs
(2018-01-01)
Guo, Jyh-Chyurn
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Yeh, Kuo-Liang
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A new compact model has been developed in this paper for accurate simulation of RF noise and extraction of actual intrinsic noise in sub-40 nm multi-finger nMOSFETs. This model can predict and verify the excess noise sources before and after deembedding, the mechanism responsible for the complicated layout dependence in various noise parameters, and facilitate optimization design for low noise devices and circuits in nanoscale CMOS technology.
A New Method for Layout-Dependent Parasitic Capacitance Analysis and Effective Mobility Extraction in Nanoscale Multifinger MOSFETs
(2011-09-01)
Yeh, Kuo-Liang
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Guo, Jyh-Chyurn
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The impact of layout-dependent parasitic capacitances on extraction of inversion carrier density Q(inv) and effective mobility mu(eff) has been investigated on multifinger MOSFETs. An improved open deembedding method can eliminate the extrinsic parasitic capacitance, and 3-D interconnect simulation is necessary for extraction of intrinsic parasitic capacitances such as gate finger sidewall and finger-end fringing capacitances, i.e., C(of) and C(f(poly-end)), respectively. Both categories of parasitic capacitance lead to overestimated Q(inv) and underestimated mu(eff). The increase in effective channel width W(eff) due to Delta W from shallow trench isolation (STI) top-corner rounding may compensate mu(eff) degradation due to STI stress. The tradeoff between mu(eff) and W(eff) determines the impact of width scaling on I(DS) and G(m). A new method based on the measured S-parameters, open-M1 deembedding, and Raphael simulation can precisely determine the mentioned parameters associated with the intrinsic channel and realize accurate extraction of mu(eff) in multifinger MOSFETs with various layouts and narrow widths down to 0.125 mu m.
Flicker Noise in Nanoscale pMOSFETs with Mobility Enhancement Engineering and Dynamic Body Biases
(2009)
Yeh, Kuo-Liang
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Ku, Chih-You
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Hong, Wei-Lun
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Guo, Jyh-Chyurn
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電子工程學系及電子研究所
The uni-axial compressive strain from e-SiGe S/D combined with dynamic body biases effect on flicker noise of pMOSFETs is presented in this paper. This compressive strain contributes higher mobility but the worse flicker noise in terms of higher S(ID)/I(D)(2) becomes a potential killer to RF/analog circuits. Forward body biases (FBB) can reduce the flicker noise but the degraded body bias effect in strained pMOSFETs makes it not as efficient as the standard ones without strain. Hooge's mobility fluctuation model is adopted to explain the uni-axial strain and dynamic body biases effect on flicker noise. The increase of Hooge parameter alpha(H) is identified the key factor responsible the degraded flicker noise in strained pMOSFETs.
Invalidation of Atorvastatin Patent Highlights Complex Chinese Patent Law
(2016-11)
Chen, Feng-Chi
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Yeh, Kuo-Liang
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生物科技學系
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Department of Biological Science and Technology
Layout-Dependent Stress Effect on High-Frequency Characteristics and Flicker Noise in Multifinger and Donut MOSFETs
(2011-09-01)
Yeh, Kuo-Liang
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Guo, Jyh-Chyurn
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The impact of MOSFET layout-dependent stress on high-frequency performance and flicker noise has been investigated. The proposed donut MOSFETs demonstrate the advantages over the standard multifinger MOSFETs, such as the lower flicker noise S(ID)/I(DS)(2) in the low-frequency domain and the higher cutoff frequency f(T) in the very high-frequency region. The elimination of the transverse stress sigma(perpendicular to) from shallow trench isolation (STI) and the suppression of interface traps along the STI edge are proposed as the primary factors responsible for the enhancement of the effective mobility mu(eff), as well as f(T), and the reduction of flicker noise. The significantly lower flicker noise realized by donut devices suggests the reduction of STI-generated traps and the suppression of mobility fluctuation due to eliminated transverse stress. The former is applied to n-channel MOS in which the flicker noise is determined by the number-fluctuation model. The latter is responsible for p-channel MOS whose flicker noise is dominated by the mobility-fluctuation model.
Low Frequency Noise in Nanoscale pMOSFETs with Strain Induced Mobility Enhancement and Dynamic Body Biases
(2009)
Yeh, Kuo-Liang
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Ku, Chih-You
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Hong, Wei-Lun
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Guo, Jyh-Chyurn
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電子工程學系及電子研究所
Local strain effect on low frequency noise (LFN) of pMOSFETs with gate length down to 60 nm was investigated in this paper. Novel and interesting results were identified from the pMOSFETs adopting embedded SiGe (e-SiGe) in source/drain for uni-axial compressive stress. This local compressive strain can realize significant mobility enhancement and desired current boost in nanoscale pMOSFETs. However, the dramatic increase of LFN emerges as a penalty traded off with mobility enhancement. The escalated LFN may become a critical killer to analog and RF circuits. Forward body biases (FBB) can improve the effective mobility (mu(eff)) and reduce LFN attributed to reduced normal field (E(eff)). However, the benefit from FBB becomes insignificant in strained pMOSFETs with sub-100 nm gate length.
Narrow-Width Effect on High-Frequency Performance and RF Noise of Sub-40-nm Multifinger nMOSFETs and pMOSFETs
(2013-01-01)
Yeh, Kuo-Liang
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Guo, Jyh-Chyurn
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The impact of narrow-width effects on high-frequency performance like f(T), f(MAX), and RF noise parameters, such as NFmin and R-n, in sub-40-nm multifinger CMOS devices is investigated in this paper. Narrow-oxide-diffusion (OD) MOSFET with smaller finger width and larger finger number can achieve lower R-g and higher f(MAX). However, these narrow-OD devices suffer f(T) degradation and higher NFmin, even with the advantage of lower R-g. The mechanisms responsible for the tradeoff between different parameters will be presented to provide an important guideline of multifinger MOSFET layout for RF circuit design using nanoscale CMOS technology.
The Impact of Layout-Dependent STI Stress and Effective Width on Low-Frequency Noise and High-Frequency Performance in Nanoscale nMOSFETs
(2010-11-01)
Yeh, Kuo-Liang
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Guo, Jyh-Chyurn
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The impact of channel width scaling on low-frequency noise (LFN) and high-frequency performance in multifinger MOSFETs is reported in this paper. The compressive stress from shallow trench isolation (STI) cannot explain the lower LFN in extremely narrow devices. STI top corner rounding (TCR)-induced Delta W is identified as an important factor that is responsible for the increase in transconductance G(m) and the reduction in LFN with width scaling to nanoscale regime. A semi-empirical model was derived to simulate the effective mobility (mu(eff)) degradation from STI stress and the increase in effective width (W(eff)) from Delta W due to STI TCR. The proposed model can accurately predict width scaling effect on G(m) based on a tradeoff between mu(eff) and W(eff). The enhanced STI stress may lead to an increase in interface traps density (N(it)), but the influence is relatively minor and can be compensated by the W(eff) effect. Unfortunately, the extremely narrow devices suffer f(T) degradation due to an increase in C(gg). The investigation of impact from width scaling on mu(eff), G(m), and LFN, as well as the tradeoff between LFN and high-frequency performance, provides an important layout guideline for analog and RF circuit design.
The Impact of MOSFET Layout Dependent Stress on High Frequency Characteristics and Flicker Noise
(2010)
Yeh, Kuo-Liang
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Ku, Chih-You
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Guo, Jyh-Chyurn
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Layout dependent stress in 90 nm MOSFET and its impact on high frequency performance and flicker noise has been investigated. Donut MOSFETs were created to eliminate the transverse stress from shallow trench isolation (STI). Both NMOS and PMOS can benefit from the donut layout in terms of higher effective mobility mu(eff) and cutoff frequency f(T), as well as lower flicker noise. The measured flicker noise follows number fluctuation model for NMOS and mobility fluctuation model for PMOS, respectively. The reduction of flicker noise suggests the reduction of STI generated traps and the suppression of mobility fluctuation due to eliminated transverse stress using donut structure.
The Impact of Uni-axial Strain on Low Frequency Noise in Nanoscale p-Channel Metal-Oxide-Semiconductor Field Effect Transistors under Dynamic Body Biases
(2010-08-01)
Yeh, Kuo-Liang
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Ku, Chih-You
;
Guo, Jyh-Chyurn
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The impact of local strain on low frequency noise (LFN) in p-channel metal-oxide-semiconductor field effect transistor (pMOSFET) is investigated under dynamic body biases For 60 nm pMOSFET, the uni-axial compressive strain from embedded SiGe (e-SiGe) in source/drain can contribute 75% effective mobility (mu(eff)) enhancement and the proportional improvement in current (I(DS)) as well as transconductance (G(m)) However, the strained pMOSFET suffer more than 80% higher LFN (S(ID)/I(D)(2)) compared with the control pMOSFET free from strain engineering The measured LFN can be consistently explained by mobility fluctuation model and the increase of Hooge parameter (alpha(H)) appears as a key factor responsible for the higher LFN in strained pMOSFET Forward body biases (FBB) is proposed as an effective method adapted to nanoscale devices for improving mu(eff) and suppressing LFN, without resort to strain engineering (C) 2010 The Japan Society of Applied Physics
The Impact of Uniaxial Strain on Flicker Noise and Random Telegraph Noise of SiC Strained nMOSFETs in 40nm CMOS Technology
(2011-01-01)
Yeh, Kuo-Liang
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Chang, Chih-Shiang
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Guo, Jyh-Chyurn
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The impact of uniaxial strain on flicker noise and random telegraph noise (RTN) was investigated in frequency and time domains, respectively. Both control and SiC strained nMOS reveal flicker noise dominated by number fluctuation model but the latter one with uniaxial strain suffers significantly higher noise. RTN measured from SiC strained nMOS features a complex spectrum with multi-level drain current fluctuation amplitudes. The capture time (tau(c)), emission time (tau(e)), and effective trap depth (Z(eff)) can be extracted to explore the impact from the uniaxial strain on trap properties, RTN, and flicker noise.
The Impact of Uniaxial Strain on Low Frequency Noise of Nanoscale PMOSFETs with e-SiGe and i-SiGe Source/Drain
(2010)
Yeh, Kuo-Liang
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Hong, Wei-Lun
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Guo, Jyh-Chyurn
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交大名義發表
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National Chiao Tung University
The Impact of Uniaxial Strain on Low Frequency Noise of Nanoscale PMOSFETs with e-SiGe and i-SiGe Source/Drain
(2010-01-01)
Yeh, Kuo-Liang
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Hong, Wei-Lun
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Guo, Jyh-Chyum
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The impact of uni-axial strain from embedded SiGe in recessed S/D (e-SiGe) and Ge implanted S/D (i-SiGe) on effective mobility mu(eff), gate leakage current, short channel effect (SCE) and low frequency noise (LFN) in pMOS has been investigated. The e-SiGe can realize superior mu(eff) enhancement but lead to worse SeE and LFN. The i-SiGe can reduce SeE and LFN but suffers limited mu(eff) improvement. Mobility fluctuation model can explain the trade-off and forward body biases (FBB) method can overcome the trade-off. SiGe strain combined with FBB is an effective solution in nanoscale pMOS to enhance RF and analog performance.