Browsing by Author "Yen, Shiang-Shiou"

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Amorphous Titanium Oxide Semiconductors on Quasi-Crystal-Like InGaZnO Channels for Thin Film Transistor Applications
(2015-06)
Hsu, Hsiao-Hsuan
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Chiou, Ping
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Cheng, Chun-Hu
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Yen, Shiang-Shiou
;
Tung, Chien-Hung
This paper reports an InGaZnO thin-film transistor with titanium-oxide semiconductor as channel capping layer. Based on the experimental results, the titanium-oxide semiconductor has the function of not only a surface passivation layer to reduce the defect states localized at grain boundaries near source/drain contacts, but also a mobility booster to enhance electric field across channel. Compared to control IGZO TFT, the crystalline IGZO TFTs with titanium-oxide semiconductor exhibits an improved performance of a low drive voltage of <5 V, a low threshold voltage of 1.9 V, a low sub-threshold swing of 244 mV/decade, and a high mobility of 13.7 cm(2)/V s. The simple titanium-oxide capping process have been demonstrated in this work, which provides considerable potential for further display applications requiring a low power operation and a low-temperature fabrication.
Bipolar Conduction in Tin-Oxide Semiconductor Channel Treated by Oxygen Plasma for Low-Power Thin-Film Transistor Application
(2016-03)
Chen, Po-Chun
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Wu, Yung-Hsien
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Zheng, Zhi-Wei
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Chiu, Yu-Chien
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Cheng, Chun-Hu
In this paper, we investigated the bipolar conduction mechanism in thin-film transistors (TFTs) with oxygen plasma treatment on tin-oxide channel. The optimized p-type thin-oxide TFTs showed an on/off ratio of >10(4), a threshold voltage of -1.05 V, and a field-effect mobility of 2.14 cm(2).V-1.s(-1). By increasing the exposure time of oxygen plasma, excess oxygen was incorporated to thin-oxide channel and converted thin monoxide to oxygen-rich n-type thin dioxide, which in turn led to n-type operation. It indicated that oxygen plasma was the critical factor to determine oxygen concentration, oxygen vacancies, metal ions and channel polarity. This proposed oxygen-content tuning through plasma treatment approach shows great promise in simplification of TFT process that can achieve n-type and p-type TFTs under the same device process.
Correlation of thermal annealing effect, crystallinity and electrical characteristics in c-axis crystallized InGaZnO thin-film transistors
(2015-09-15)
Hsu, Hsiao-Hsuan
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Yen, Shiang-Shiou
;
Chiu, Yu-Chien
;
Chiou, Ping
;
Chang, Chun-Yen
A low off-state current of 1.6 x 10(-14) A/mu m and a small subthreshold gate swing of 152 mV/decade were achieved in a novel thin film transistor using a c-axis crystallized InGaZnO semiconductor that could be obtained at a low substrate temperature range of 150 degrees C. From experimental results, we found that the lowered off-state current is mainly attributed to the formation of rich Ga-O bonds to reduce oxygen vacancies, and the c-axis crystallized structure of IGZO to increase the potential barrier on the source side due to the increase of local trap states at the grain boundary. (C) 2015 Elsevier B.V. All rights reserved.
Gettering Effect Induced by Oxygen-Deficient Titanium Oxide in InZnO and InGaZnO Channel Systems for Low-Power Display Applications
(2016-03)
Yen, Shiang-Shiou
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Chiu, Yu-Chien
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Cheng, Chun-Hu
;
Chen, Po-Chun
;
Yeh, Yu-Chen
This paper reported the IGZO and IZO thin-film transistor (TFT) with titanium-oxide semiconductor as channel capping layer. After the TiOx Gettering process, the oxygen vacancies in IGZO channel were successfully modified to maximize the carrier concentration and device mobility. The superior transfer characteristics included a low sub-threshold swing of 79 mV/decade, a very high mobility of 68 cm(2)/V.s, and good on/off-current ratio of 5.61 x 10(6). However, the IZO channel with nano-crystallized grains and without Ga atom doping showed unfavorable transistor characteristics. In addition to apparently degraded transfer properties, the spontaneously oxidized TiOx capping layer also lead to an increase of channel parasitic resistance that limits the output driving current. Therefore, we believe that the existence of Ga-O bonds among IGZO channel would be helpful to stabilize oxygen diffusion behavior and electric structure during Gettering process.
High holding voltage segmentation stacking silicon-controlled-rectifier structure with field implant as body ties blocking layer
(2016-04)
Yen, Shiang-Shiou
;
Cheng, Chun-Hu
;
Lan, Yu-Pin
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Chiu, Yu-Chien
;
Fan, Chia-Chi
High electrostatic discharge (ESD) protection robustness and good transient-induced latchup immunity are two important issues for high voltage integrate circuit application. In this study, we report a high-voltage-n-type-field (HVNF) implantation to act as the body ties blocking layer in segmented topology silicon-controlled-rectifier (SCR) structure in 0.11 mu m 32 V high voltage process. This body ties blocking layer eliminate the elevated triggered voltage in segmented technique. Using a large resistance as shunt resistor in resistor assisted triggered SCRs stacking structure, the double snapback phenomenon is eliminate. The series SCR could be decoupled a sufficient voltage drop to turned-on when a very low current flow through the shunt resistor. The holding voltage and the failure current of 22 V and 3.4 A are achieved in the best condition of segmented topology SCR stacking structure, respectively. It improves the latchup immunity at high voltage ICs application. On the other hand, the triggered voltage almost keep the same value which is identical to SCR single cell without using segmented topology. (C) 2016 The Japan Society of Applied Physics
High holding voltage segmentation stacking silicon-controlled-rectifier structure with field implant as body ties blocking layer
(2016-04-01)
Yen, Shiang-Shiou
;
Cheng, Chun-Hu
;
Lan, Yu-Pin
;
Chiu, Yu-Chien
;
Fan, Chia-Chi
High electrostatic discharge (ESD) protection robustness and good transient-induced latchup immunity are two important issues for high voltage integrate circuit application. In this study, we report a high-voltage-n-type-field (HVNF) implantation to act as the body ties blocking layer in segmented topology silicon-controlled-rectifier (SCR) structure in 0.11 mu m 32 V high voltage process. This body ties blocking layer eliminate the elevated triggered voltage in segmented technique. Using a large resistance as shunt resistor in resistor assisted triggered SCRs stacking structure, the double snapback phenomenon is eliminate. The series SCR could be decoupled a sufficient voltage drop to turned-on when a very low current flow through the shunt resistor. The holding voltage and the failure current of 22 V and 3.4 A are achieved in the best condition of segmented topology SCR stacking structure, respectively. It improves the latchup immunity at high voltage ICs application. On the other hand, the triggered voltage almost keep the same value which is identical to SCR single cell without using segmented topology. (C) 2016 The Japan Society of Applied Physics
Interface Polarization Fluctuation Effect of Ferroelectric Hafnium-Zirconium-Oxide Ferroelectric Memory with Nearly Ideal Subthreshold Slope
(2015)
Chiu, Yu-Chien
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Cheng, Chun-Hu
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Fan, Chia-Chi
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Chen, Po-Chun
;
Chang, Chun-Yen
Investigation of Double-Snapback Characteristic in Resistor-Triggered SCRs Stacking Structure
(2017-10-01)
Yen, Shiang-Shiou
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Cheng, Chun-Hu
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Fan, Chia-Chi
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Chiu, Yu-Chien
;
Hsu, Hsiao-Hsuan
Achieving high latch-up immunity is critical for power-rail electrostatic discharge (ESD) clamp circuits in high-voltage (HV) integrated circuit products. To investigate how shunt resistance affects the transmission line pulsing current-voltage characteristics of resistance-triggered stacked silicon controlled rectifiers (SCRs), a lateral SCR (LSCR) and a modified LSCR were combined in several SCR stacked structures with various shunt resistances. Compared with in tradition stacked ESD cells, the snapback margin of the SCRs does not expand and can even be reduced. A high holding voltage of 33.4 V is achieved using the resistance-triggered stacked SCR technique in a 0.11 mu m32-V HV process. A trigger voltage of approximately 51 V and a failure current of 3.3 A is achieved in this experiment. According to theorem analysis based on a voltage decoupling equation, the minimum trigger voltage can probably be further reduced to 46 V by using the resistance-triggered stacked SCR technique. This paper can offer a simple guideline for designing ESD protection circuit using the resistor-triggered SCRs stacking structure.
Low Power 1T DRAM/NVM Versatile Memory Featuring Steep Sub-60-mV/decade Operation, Fast 20-ns Speed, and Robust 85 degrees C-Extrapolated 10(16) Endurance
(2015)
Chiu, Yu-Chien
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Cheng, Chun-Hu
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Chang, Chun-Yen
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Lee, Min-Hung
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Hsu, Hsiao-Hsuan
In this work, we report a one-transistor (1T) versatile memory; the memory transistor characteristics achieve sub-60-mV/dec operation and considerably low off-state leakage of 10(-15) A/mu m at a supply voltage below 0.5V. The versatile memory features DRAM/NVM functions of large Delta V-T window of 2.8V, fast 20-ns speed, 10(3)s retention at 85 degrees C, and long extrapolated 10(16) endurance at 85 degrees C, which show the potential for 3D memory application with severe requirement on both high density and low power consumption.
On the Variability of Threshold Voltage Window in Gate-Injection Versatile Memories with Sub-60mV/dec Subthreshold Swing and 10(12)-Cycling Endurance
(2016)
Chiu, Yu-Chien
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Chang, Chun-Yen
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Yen, Shiang-Shiou
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Fan, Chia-Chi
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Hsu, Hsiao-Hsuan
Incorporating a charge-trapped ZrSiO with ferroelectric HfZrO dielectrics, we demonstrated a gate-injection versatile memory with sub-60mV/dec subthreshold swing (SS) and large threshold voltage window (Delta V-T) of >2V under a fast 20-ns speed. Moreover, it is revealed that the local defects at ZrSiO/HfZrO interface affect the ferroelectric negative capacitance tuning and thus increases the variability of V-T and SS during 10(12) cycling endurance.
Structural and electrical characteristics of thin film transistor employing an oriented crystalline InGaZnO channel
(2015-04-01)
Yen, Shiang-Shiou
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Hsu, Hsiao-Hsuan
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Chiou, Ping
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Cheng, Chun-Hu
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Tung, Chien-Hung
In this study, we investigate the impact of orientated crystalline InGaZnO (IGZO) thin film transistor. To evaluate interface thermodynamic stability of temperature-sensitive IGZO film, the film-structural stabilities of high-and low-indium-content InGaZnO were studied. With increasing annealing temperature up to 700 degrees C, the crystallinity becomes more pronounced while device electrical characteristics are further improved. We find that the apparently reduced off-state current can be attributed to the formation of c-axis-orientated crystalline located at the X-ray diffraction peak of (0, 0, 16). The performance improvements include a very low turn-on voltage close to zero voltage, a small subthreshold swing of 130mV/dec, and a low off-state current of 2.4 x 10(-14)A/mu m at a low operating voltage of 4V. (C) 2015 The Japan Society of Applied Physics
Temperature-dependent characteristics of junctionless bulk transistor
(2013-09-23)
Han, Ming-Hung
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Chen, Hung-Bin
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Yen, Shiang-Shiou
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Shao, Chi-Shen
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Chang, Chun-Yen
The temperature-dependent performance, including drain current (I-d) and gate capacitance (C-gg) of multi-gate junctionless (JL) bulk transistor for temperature (T) ranging from 150 K to 500 K, was investigated using 3D thermodynamic quantum-corrected device simulation. The combination effect of impurity scattering and phonon scattering is observed owing to the different temperature-dependent of mobility at low and high temperature. Since the C-gg of the JL device consists of a series combination of oxide capacitance (C-ox) and semiconductor channel capacitance (C-S) due to bulk conduction of the current, the C-gg at on-state (V-g = 1 V) shows much sensitive to the temperature than a conventional inversion-mode transistor. (C) 2013 AIP Publishing LLC.
Temperature-Dependent Transfer Characteristics of Low Turn-On Voltage InGaZnO Metal-Oxide Devices With Thin Titanium Oxide Capping Layers
(2015-06)
Hsu, Hsiao-Hsuan
;
Cheng, Chun-Hu
;
Chiou, Ping
;
Chiu, Yu-Chien
;
Yen, Shiang-Shiou
This paper reports an InGaZnO thin-film transistor involving a wide bandgap gate dielectric of ZrO2 and IGZO/TiOx channel stack. According to our experimental results, the IGZO TFT with a thin TiOx channel capping layer shows good device integrity of a low threshold voltage of 0.37 V, a small sub-threshold swing of 77 mV/decade, and a high mobility of 33 cm(2)/V.s under a low drive voltage of < 2 V. We also demonstrate that the significantly improved electrical property is mainly contributed by the enhanced channel electric field after TiOx capping, associated with maximizing charge accumulated capability. The favorable high-temperature transfer characteristics are also obtained in IGZO/TiOx TFT, indicating a weak Fermi-level pinning in IGZO/TiOx channel structure. With the operating temperature increasing further, the thermal activated effect shall dominate IGZO channel property beyond percolation conduction.