Browsing by Author "Yoo, WJ"

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3D GOI CMOSFETs with novel IrO2(Hf) dual gates and high-kappa dielectric on 1P6M-0.18 mu m-CMOS
(2004)
Yu, DS
;
Chin, A
;
Laio, CC
;
Lee, CF
;
Cheng, CF
For the first time, we demonstrate 3D integration of self-aligned IrO2(Hf)/LaAlO3/GOI CMOSFETs above 0.18 pm Si CMOSFETs. At EOT=1.4nm, the novel IrO2(Hf) dual gates (4.4 and 5.1 eV workfunction) on control 2D LaAlO3/Si devices have high electron and hole mobilities of 203 and 67 cm(2)/Vs. On the 3D structure the LaAlO3/GOI shows even higher 389 and 234 cm(2)/Vs mobilities, and process compatibility with current Si VLSI. The higher drive current, larger integration density, shorter interconnects distance, and simple process of 3D approach can help solve the AC power issue and 2D scaling limitation.
A novel program-erasable high-(K) A1N-Si MIS capacitor
(2005-03-01)
Lai, CH
;
Chin, A
;
Hung, BF
;
Cheng, CF
;
Yoo, WJ
We demonstrate a programmable-erasable MIS capacitor with a single layer high-kappa AIN dielectric on Si having a high capacitance density of 5 fF/mum(2). It has low program and erase voltages of +4 and -4 V, respectively. Such an erase function is not available in other single layer Al2O3, AION, or other known high-kappa dielectric capacitors, where the threshold voltage (T h) shifts continuously with voltage. This device exhibits good data retention with a V-th change of only 0.06 V after 10 000 s.
Formation of dual-phase HfO2-HfxSi1-xO2 dielectric and its application in memory devices
(2005-07-01)
Wang, YQ
;
Chen, JH
;
Yoo, WJ
;
Yeo, YC
;
Yeo, YC
In this paper, we studied the phase-separation phenomenon of Hf0.5Si0.5O2 film deposited on SiO2 or sandwiched by SiO2, by x-ray photoelectron spectroscopy and transmission electron microscopy. The Hf0.5Si0.5O2 film underwent phase separation to form a doublet-phase HfO2-HfxSi1-xO2 (x < 0.5) film, and was used as a trapping layer in a metal-blocking oxide-silicon nitride-tunnel oxide-silicon-type memory structure, where the dual-phase HfO2-HfxSi1-xO2 (DPHSO) film replaces the conventional silicon nitride (Si3N4) trapping layer. The charge storage properties of the DPHSO film were investigated and compared with HfO2 and Si3N4. It was found that for a given electric field applied to the tunnel oxide, the programming speed of memory devices using a DPHSO or HfO2 film as a trapping layer is faster than that using SiA. This indicates the higher electron-capture efficiency of the DPHSO and HfO2 films. In addition, the double-phase microstructure of the DPHSO film also provided better retention property than pure HfO2. (c) 2005 American Institute of Physics.
Lanthanide and Ir-based dual metal-gate/HfAlON CMOS with large work-function difference
(2005)
Yu, DS
;
Chin, A
;
Wu, CH
;
Li, MF
;
Zhu, C
Metallic diffusion through high-K HfO(2), caused by high temperature metal-nitride decomposition, was reduced by using robust HfAlON. Useful dual effective work-function (phi(m,eff)) of 4.25 and 5.15 eV are obtained in TaTb(0.2)N/HfAlON and Ir/HfAlON at 1.7nm EOT. Good dual phi(m,eff) of 4.15 and 4.9 eV are also obtained in Yb(x)Si/HfAlON and Ir(x)Si/HfAlON FUSI-gates by reduced metal diffusion at lower temperature.
Low noise RF MOSFETs on flexible plastic substrates
(2005-07-01)
Kao, HL
;
Chin, A
;
Hung, BF
;
Lee, CF
;
Lai, JM
We report a low minimum noise figure (NFmin) of 1.1 dB and high associated gain (12 dB at 10 GHz) for 16 gate-finger 0.18-mu m RF MOSFETs, after thinning down the Si substrate to 30 mu m and mounting it on plastic. The device performance was improved by flexing the substrate to create stress, which produced a 25% enhancement of the saturation drain current and lowered NFmin to 0.92 dB at 10 GHz. These excellent results for mechanically strained RF MOSFETs on plastic compare well with 0.13-mu m node (L-g = 80 nm) devices.
Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectric and metal gate electrode
(2004-10-01)
Zhu, SY
;
Yu, HY
;
Chen, JD
;
Whang, SJ
;
Chen, JH
Both P- and N-channel MOSFET's with Schottky barrier silicide source/drain (S/D), high-K gate dielectric and metal gate were successfully fabricated using a simplified low temperature process. The highest temperature after the high-K dielectric formation is 420degreesC. PMOSFETs with PtSi S/D show excellent electrical performance of an I-on/I-off similar to 10(7)-10(8) and a subthreshold slope of 66 mV/dec, similar to those formed by a normal process with an optimized sidewall spacer. NMOSFETs with DySi2-x S/D have similar to3 orders of magnitude larger I-off than that of PMOSFETs and show two slopes in the subthreshold region, resulting in the I-on/I-off similar to 10(5) at low drain voltage. It can be attributed to the relatively higher barrier height (Phi(n)) of DySi2-x/n-Si than that of PtSi/p-Si (Phi(p)) and the rougher DySi2-x film. Adding a thin intermediate Ge layer (similar to1nm) between Dy and Si can improve the film morphology significantly. As a result, the improved performance of N-MOSFET is observed. (C) 2004 Published by Elsevier Ltd.
Low voltage high speed SiO(2)/AlGaN/AlLaO(3)/TaN memory with good retention
(2005)
Chin, A
;
Laio, CC
;
Chen, C
;
Chiang, KC
;
Yu, DS
To improve trapping using deeper well AlGaN (chi=3.8eV), lower voltage drop in high-K AlLaO(3) barrier (kappa=23), and smaller erase current by large Delta E(c) of AILaO(3)/TaN, the SiO(2)/AlGaN/AlLaO(3)/TaN devices show good 85 degrees C memory integrity of low +/- 10V 1ms P/E, large 3.9V initial Delta V(th) and 2.4V extrapolated 10-year retention. A fast 100ps P/E of +/- 11V still gives 3.0V initial Delta V(th) and 1.6V 10-year retention.
Novel SiO2/AlN/HfAlO/IrO2 memory with fast erase, large triangle V-th and good retention
(2005)
Lai, CH
;
Chin, A
;
Chiang, KC
;
Yoo, WJ
;
Cheng, CF
Using the strong trapping capability of novel AlN (kappa=10), low voltage drop in high-kappa layers and high workfunction IrO2 with low leakage current, the SiO2/AlN/HfAlO(K=17)/IrO2 device shows good 85 degrees C memory integrity of fast 100 is erase, large 3.7V Delta V-th and 1.9V extrapolated memory window for 10-year retention at low 13V program/erase. These increase to 5.5V Delta V-th and 3.4V for 85 degrees C 10-year retention at 1 ms erase.
Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode
(2004-05-01)
Zhu, SY
;
Yu, HY
;
Whang, SJ
;
Chen, JH
;
Shen, C
This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-kappa gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi source/drain (S/D), excellent electrical performance of I-on/I-off similar to 10(7) - 10(8) and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi2-x S/D, I-on/I-off can reach similar to 10(5) at V-ds of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-kappa dielectric and metal-gate materials to be used in the future generation CMOS technology.
Three-dimensional metal gate-high-kappa-GOI CMOSFETs on 1-poly-6-metal 0.18-mu m Si devices
(2005-02-01)
Yu, DS
;
Chin, A
;
Liao, CC
;
Lee, CF
;
Cheng, CF
We demonstrate three-dimensional (3-D) self-aligned [IrO2-IrO2-Hf]-LaAlO3-Ge-on-Insulator (GOI) CMOSFETs above 0.18-mum Si CMOSFETs for the first time. At an equivalent oxide thickness of 1.4 nm, the 3-D IrO2-LaAlO3-GOI p-MOSFETs and IrO2-Hf-LaAlO3-GOI nMOSFETs show high hole and electron mobilities of 234 and 357 cm(2)/Vs respectively, without depredating the underneath 0.18-mum Si devices. The hole mobility is 2.5 times higher than the universal mobility, at 1 MV/cm effective electric field. These promising results are due to the low-temperature GOI device process, which is well-matched to the low thermal budget requirements of 3-D integration. The high-performance GOI devices and simple 3-D integration process, compatible to current very large-scale integration (VLSI) technology, should be useful for future VLSI.