Browsing by Author "You, Wei-Xiang"

Now showing 1 - 15 of 15

A Compact Subthreshold Model for Short-Channel Monolayer Transition Metal Dichalcogenide Field-Effect Transistors
(2016-07)
You, Wei-Xiang
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This brief presents a compact subthreshold model for short-channel monolayer transition metal dichalcogenide (TMD) field-effect transistors. In this model, the impact of fringe fields from the high-K gate dielectric is considered and incorporated into a new characteristic-length expression using a single model parameter. This model has been verified with 2-D numerical simulations for TMD devices with gate length down to 5.9 nm based on ITRS 2028 low-power technology node.
A New 8T Hybrid Nonvolatile SRAM With Ferroelectric FET
(2020-01-01)
You, Wei-Xiang
;
Su, Pin
;
Hu, Chenming
;
電子工程學系及電子研究所
;
國際半導體學院
This paper proposes a new 8T nonvolatile SRAM (nvSRAM) cell employing ULP FinFETs and ferroelectric FinFETs to enable energy-efficient and low-latency store/recall operations. Different from other types of nvSRAM requiring additional circuitry or nonvolatile memories connected to a standard 6T SRAM cell to achieve nonvolatility, the proposed hybrid nvSRAM cell reduces the area penalty by embedding the nonvolatile ferroelectric FinFETs in a 6T SRAM cell without sacrificing the cell stability, read/write performance and power consumption.
Depolarization Field in Ferroelectric Nonvolatile Memory Considering Minor Loop Operation
(2019-09-01)
You, Wei-Xiang
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This letter investigates the depolarization field in a metal-ferroelectric-metal-insulator-metal (MFMIM) nonvolatile memory (NVM) considering the minor hysteresis loop operation. Our study indicates that, different from previous studies merely considering the major loop operation, the depolarization field for the ferroelectric undergoing the minor loop increases with decreasing oxide thickness. In other words, in addition to suppressing the gate leakage, thicker oxide thickness is favorable to lower the depolarization field and improves the retention for a given memory window (MW). This letter may provide insights for device design of ferroelectric nonvolatile memories.
Design Space Exploration Considering Back-Gate Biasing Effects for 2D Negative-Capacitance Field-Effect Transistors
(2017-08-01)
You, Wei-Xiang
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
With the aid of an analytical and scalable model, this paper explores the design space for negative-capacitance (NC) field-effect transistors (FETs) with a 2D semiconducting transition-metal-dichalcogenide channel. In addition, the impact of back-gate biasing on the design space and the body effect of 2D-NCFETs is also investigated. Our study indicates that, to mitigate the conflict between subthreshold swing and hysteresis and to maximize the design space for the 2D-NCFET, a thin buried oxide and an adequate reverse back-gatebias can be applied to achieve the optimum design.
Design Space Exploration Considering Back-Gate Biasing Effects for Negative-Capacitance Transition-Metal-Dichalcogenide (TMD) Field-Effect Transistors
(2017-01-01)
You, Wei-Xiang
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work, with the aid of an analytical and scalable model, we explore the design space for negative-capacitance (NC) FETs with a 2D semiconducting transition-metal-dichalcogenide (TMD) channel with emphasis on the impact of back-gate biasing. Our study indicates that, to mitigate the conflict between subthreshold swing (SS) and hysteresis and to maximize the design space for the NC-TMDFET, a thin buried oxide (BOX) and an adequate reverse back-gate bias can be applied to achieve the optimum design.
Device Structural Effects on Negative-Capacitance FETs
(2018-01-01)
Su, Pin
;
You, Wei-Xiang
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper discusses several device structural effects on negative-capacitance FETs (NCFETs) with emphasis on the wide-range average subthreshold swing. We point out and explain the intrinsic difference between SOI and double-gate 2D NCFETs. The impact of drain coupling on the NC effect and its implication on the design of short-channel NC-FinFETs are also addressed.
Device Structural Effects, SPICE Modeling and Circuit Evaluation for Negative-Capacitance FETs
(2019-01-01)
Su, Pin
;
You, Wei-Xiang
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Electrostatic Integrity in Negative-Capacitance FETs - A Subthreshold Modeling Approach
(2019-01-01)
Su, Pin
;
You, Wei-Xiang
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Using an analytical subthreshold potential model, this paper shows that the negative-capacitance FinFET (NC-FinFET) inherently possesses a superior electrostatic integrity than the baseline FinFET. Taking into account the spacer induced distributed charges in our subthreshold model, we demonstrate that an adequate spacer design can be utilized to further enhance the NC effect and the electrostatic integrity for NC-FinFETs. This may serve as a way to extend the FinFET scaling.
Evaluation of 2D Negative-Capacitance FETs for Low-Voltage SRAM Applications
(2019-01-01)
Tseng, Kuei-Yang
;
You, Wei-Xiang
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work, we comprehensively evaluate and analyze the stability and performance of 6T SRAM cells using 2D MFIS-type negative capacitance FETs (2D-NCFETs) based on the IRDS 2030 node with 10-nm gate length. Our results indicate that 2D-NCFETs possess better RSNM than the 2D-FET counterpart under low supply voltages. Our study also shows that 2D-NCFETs have better WSNM except for V-DD = 0.2V due to the existence of hysteresis loop in write curve during write operation. By using write-assist circuits or back-gating techniques, we demonstrate that the WSNM of 2D-NCFETs can be significantly improved. We further analyze the performance of read and write operations, and 2D-NCFETs have been found to possess better performance than 2D-FETs.
Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits
(2019-04-01)
You, Wei-Xiang
;
Su, Pin
;
Hu, Chenming
;
電子工程學系及電子研究所
;
國際半導體學院
This paper examines metal-ferroelectric-insulator-semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse V-ds-dependence of threshold voltage (V-T), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low V-DD.
Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits Using SPICE Simulation
(2018-01-01)
You, Wei-Xiang
;
Su, Pin
;
Hu, Chenming
;
電子工程學系及電子研究所
;
國際半導體學院
This work examines the metal-ferroelectricinsulator-semiconductor (MFIS) negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. With the aid of a short-channel NC-FinFET compact model, we confirm the functionality and determine the standby-power/switching-energy/delay performance of logic circuits (5-stage inverter and 4-bit Manchester carry-chain (MCC) adder) employing 14nm ULP NC-FinFETs versus FinFETs. We show that the inverse V-ds-dependency of threshold voltage (V-T), also known as the negative DIBL, of NCFET is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTI.) circuits, especially for the PTI, at low V-DD.
Intrinsic Difference Between 2-D Negative-Capacitance FETs With Semiconductor-on-Insulator and Double-Gate Structures
(2018-10-01)
You, Wei-Xiang
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
With the aid of an analytical and general model, this paper investigates the intrinsic difference in the negative-capacitance (NC) effect and design space between semiconductor-on-insulator(SOI) and double-gate (DG) metal-ferroelectric-insulator-semiconductor-type NC field-effect transistors (NCFETs) with a 2-D semiconducting transition-metal-dichalcogenide channel (2-D NCFET). By examining the distributions of internal charge, voltage gain, and capacitance matching over the whole bias range, the intrinsic difference in NC effects between these two topologies is pointed out and explained. Our study indicates that for an intrinsic DG 2-D NCFET, it is difficult to achieve sub-2.3 kT/q average subthreshold swing (SS). By contrast, the bias-dependent subthreshold internal charge and larger curvature of ferroelectric capacitance due to the independent backgate in the SOI 2-D NCFET enable larger design space and sub-2.3 kT/q average SS, making it more suitable for low-power applications.
Investigation and Comparison of Design Space for Ultra-Thin-Body GeOI/SOI Negative Capacitance FETs
(2017-01-01)
Lee, Ho-Pei
;
Yu, Chien-Lin
;
You, Wei-Xiang
;
Su, Pin
;
電子工程學系及電子研究所
Investigation of Short-Channel Effects in 2D Negative-Capacitance Field-Effect Transistors
(2017-01-01)
You, Wei-Xiang
;
Tsai, Chih-Peng
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work, the short-channel effects (SCEs) in negative-capacitance FETs with 2D-material channel (2D-NCFET) are systematically investigated through numerical simulation corroborated by a theoretical 2D-NCFET subthreshold model. Our study reveals that, due to the impact of drain coupling on the negative-capacitance effect, the 2D-NCFET exhibits distinct SCEs. Additionally, for a given equivalent oxide thickness (EOT), the dielectric constant of the high-K interlayer can significantly alter the subthreshold characteristics of the short-channel 2D-NCFETs.
Short-Channel Effects in 2D Negative-Capacitance Field-Effect Transistors
(2018-04-01)
You, Wei-Xiang
;
Tsai, Chih-Peng
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Through numerical simulations corroborated by an analytical subthreshold model considering drain coupling, this paper systematically investigates the short-channel effects in negative-capacitance FETs with 2D MoS2 channel (2D-NCFET). Our study indicates that, due to the impact of drain coupling on the negative-capacitance effect, the 2D-NCFET exhibits distinct short-channel behaviors such as improved average subthreshold swing and threshold-voltage roll-up with decreasing gate length. In addition, the fringe field through the high-k interlayer dielectric can significantly alter the subthreshold characteristics of the short-channel 2D-NCFET, and henceneeds to be carefully taken into account. Our studymay provide insights for device design using negative-capacitance FETs.