Browsing by Author "Yu, Shao-Ming"

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A compact model for electrostatic discharge protection nanoelectronics simulation
(2005)
Chou, Hung-Mu
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Yu, Shao-Ming
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Lee, Jam-Wem
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Li, Yiming
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電信工程研究所
In nanoelectronics, snapback phenomena play an important role in electrostatic discharge (ESD) protection devices, in particular for gigascale, very large scale integration (VLSI) circuit design. In this paper we present a new ESD equivalent circuit model for deep submicrion and nanoscale semiconductor device simulation. By considering the geometry effect in the formulation of snapback characteristics, our model can be directly incorporated into electronic circuit simulation for the whole chip ESD protection circuit design. With the developed ESD model, we can investigate robust enhancement problems and perform a SPICE based whole chip ESD protection circuit design in nanoelectronics.
A comparative study of foreign direct investment flow using diffusion models
(2007)
Li, Yiming
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Chiang, Yi-Hui
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Yu, Shao-Ming
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Chiang, Su-Yun
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Hung, C. -H.
In this work, we apply an improvement dynamic model of the foreign direct investment (FDI) flow to analyze the evolution of FDI flow. In comparison with the fundamental growth model of FDI, the simulation result is further accurate if the asymmetric growth pattern and heterogeneity of the potential adopters are considered. According to the result, the internal influence dominates the growth of FDI flow from Taiwan to China during 2001-2006, taking the electronics industry for example.
A coupled-simulation-and-optimization approach to nanodevice fabrication with minimization of electrical characteristics fluctuation
(2007-11-01)
Li, Yiming
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Yu, Shao-Ming
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資訊工程學系
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電信工程研究所
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Department of Computer Science
In this paper, a simulation-based optimization methodology for nanoscale complementary metal-oxide-semiconductor (CMOS) device fabrication is advanced. Fluctuation of electrical characteristics is simultaneously considered and minimized in the optimization procedure. Integration of device and process simulation is implemented to evaluate device performances, where the hybrid intelligent approach enables us to extract optimal recipes which are subject to targeted device specification. Production of CMOS devices now enters the technology node of 65 nm; therefore, random-dopant-induced characteristic fluctuation should be minimized when a set of fabrication parameters is suggested. Verification of the optimization methodology is tested and performed for the 65-nm CMOS device. Compared with realistic fabricated and measured data, this approach can achieve the device characteristics; e.g., for the explored 65-nm n-type MOS field effect transistor, the on-state current > 0.35 mA/mu m, the off-state current < 1.5e - 11 A/mu m, and the threshold voltage = 0.43 V. Meanwhile, it reduces the threshold voltage fluctuation (sigma(vth) similar to 0.017 V). This approach provides an alternative to accelerate the tuning of process parameters and benefits manufacturing of nanoscale CMOS devices.
A Novel Approach to Compact Model Parameter Extraction for Excimer Laser Annealed Complementary Thin Film Transistors
(2004-10-01)
Li, Yiming
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Yu, Shao-Ming
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資訊工程學系
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電信工程研究所
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友訊交大聯合研發中心
A unified physical-based model parameter extraction technique for excimer laser annealed lower temperature polycrystalline silicon (LTPS) complementary thin film transistors (TFTs) is for the first time proposed. For two well-known compact models of LTPS TFT, Rensselaer Polytechnic Institute (RPI) V1 and V2 models, our approach sequentially optimizes the model parameters in the regions of linear, subthreshold, saturation, and leakage. Compared with the measured results, the extracted I-D - V-G, I-D - V-D, transconductance, and output conductance are within 3% of accuracy. The agreement with the experimental data is excellent for the n- and p-type LTPS TFTs with different length and width. This extraction technique bridges the fabrication of LTPS TFTs and the design of complementary system on panel circuits.
A Quantum Correction Model for Nanoscale Double-Gate MOS Devices Under Inversion Conditions
(2003-12-01)
Li, Yiming
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Tang, Ting-Wei
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Yu, Shao-Ming
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資訊工程學系
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友訊交大聯合研發中心
A quantum correction model for nanoscale double-gate MOSFETs under inversion conditions is proposed. Based on the solution of Schrodinger-Poisson equations, the developed quantum correction model is optimized with respect to (i) the left and right positions of the charge concentration peak, (ii) the maximum of the charge concentration, (iii) the total inversion charge sheet density, and (iv) the average inversion charge depth, respectively. This model can predict inversion layer electron density for various oxide thicknesses, silicon film thicknesses, and applied voltages. Compared to the Schrodinger-Poisson results, our model prediction is within 3.0% of accuracy. This quantum correction model has continuous derivatives and is therefore amenable to a device simulator.
A quantum hydrodynamic simulation of strained nanoscale VLSI device
(2006)
Lo, Shih-Ching
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Yu, Shao-Ming
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資訊工程學系
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Department of Computer Science
Strained silicon field effect transistor (FET) has been known for enhancing carrier mobility. The stained Si channel thickness, the Si1-xGex composition fraction and the Si1-xGex layer thickness are three crucial parameters for designing strained Si/SiGe MOSFET. Mobility enhancement and device reliability may be unnecessarily conservative. In this paper, numerical investigation of drain current, gate leakage and threshold voltage for strained Si/SiGe MOSFET are simulated under different device profiles. According to our results, the optimal combination of parameters are as follows: stained Si channel thickness is 7 nm, Ge content is 20%, and the Si1-xGex layer thickness should be chosen between 20 similar to 50 nm.
A simulation-based hybrid optimization technique for low noise amplifier design automation
(2007)
Li, Yiming
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Yu, Shao-Ming
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Li, Yih-Lang
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電信工程研究所
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Institute of Communications Engineering
In this paper, a simulation-based optimization technique for integrated circuit (IC) design automation is presented. Based on a genetic algorithm (GA), Levenberg-Marquardt (LM) method, and circuit simulator, a window-interfaced prototype of computer-aided design (CAD) is developed for IC design. Considering low noise amplifier (LNA) IC, we simultaneously evaluate specifications including S parameters, K factor, noise figure, and input third-order intercept point in the optimization process. If the simulated results meet the aforementioned constraints, the prototype outputs the optimized parameters. Otherwise, CAD activates GA for global optimization; simultaneously, LM method searches solutions with the results of GA. The prototype then calls a circuit simulator to compute and evaluate newer results until all specifications are matched. More than fifteen parameters including device sizes, passive components, and biasing conditions are optimized for the aforementioned constraints. For LNA IC with 0.18 mu m metal-oxide-silicon filed effect transistors, benchmark results confirm the functionality of the implemented prototype.
A study of threshold voltage fluctuations of nanoscale double gate metal-oxide-semiconductor field effect transistors using quantum correction simulation
(2006-07-01)
Li, Yiming
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Yu, Shao-Ming
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資訊工程學系
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電信工程研究所
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Department of Computer Science
In this paper, we computationally investigate fluctuations of the threshold voltage introduced by random dopants in nanoscale double gate metal-oxide-semiconductor field effect transistors (DG MOSFETs). To calculate variance of the threshold voltage of nanoscale DG MOSFETs, a quantum correction model is numerically solved with the perturbation and the monotone iterative techniques. Fluctuations of the threshold voltage resulting from the random dopant, the gate oxide thickness, the channel film thickness, the gate channel length, and the device width are calculated. Quantum mechanical and classical results have similar prediction on fluctuations of the threshold voltage with respect to different designing parameters including dimension of device geometry as well as the channel doping. Fluctuation increases when the channel doping, the channel film thickness, and/or the gate oxide thickness increase. On the other hand, it decreases when the channel length and/or the device width increase. Calculations of the quantum correction model are quantitatively higher than that of the classical estimation according to different quantum confinement effects in nanoscale DG MOSFETs. Due to good channel controllability, DG MOSFETs possess relatively lower fluctuation, compared with the fluctuation of single gate MOSFETs (less than a half of the fluctuation[-11pc] of SG MOSFETs). To reduce fluctuations of the threshold voltage, epitaxial layers on both sides of channel with different epitaxial doping are introduced. For a certain thickness of epitaxial layers, the fluctuation of the threshold voltage decreases when epitaxial doping decreases. In contrast to conventional quantum Monte Carlo approach and small signal analysis of the Schrodinger-Poisson equations, this computationally efficient approach shows acceptable accuracy and is ready for industrial technology computer-aided design application.
A unified optimization framework for real world problems
(2006)
Li, Yiming
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Yu, Shao-Ming
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電信工程研究所
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Institute of Communications Engineering
In this paper, an object-oriented unified optimization framework (UOF) for general problem optimization is developed. Based on global evolutionary algorithms, numerical deterministic methods, and C++ objective design, the UOF itself has great potential to perform optimization operations on kind of problems. The UOF provides basic interfaces to define a general problem and generic solver;, hence the two different parts are bridged. The UOF components are categorized into problem and solver parts and work independently. Therefore, reutilization of the high level code allows an adaptation to new problem and solver quickly. We customize the UOF to deal with some real world optimization problems.
A variable coefficient method for accurate Monte Carlo simulation of dynamic asset price
(2007)
Li, Yiming
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Hung, Chih-Young
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Yu, Shao-Ming
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Chiang, Su-Yun
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Chiang, Yi-Hui
In this work, we propose an adaptive Monte Carlo (MC) simulation technique to compute the sample paths for the dynamical asset price. In contrast to conventional MC simulation with constant drift and volatility (mu,sigma) , our MC simulation is performed with variable coefficient methods for(mu,sigma)in the solution scheme, where the explored dynamic asset pricing model starts from the formulation of geometric Brownian motion. With the method of simultaneously updated (mu,sigma) , more than 5,000 runs of MC simulation are performed to fulfills basic accuracy of the large-scale computation and suppresses statistical variance. Daily changes of stock market index in Taiwan and Japan are investigated and analyzed.
An optimal silicidation technique for electrostatic discharge protection sub-100 nm CMOS devices in VLSI circuit
(2007-02-01)
Yu, Shao-Ming
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Lee, Jam-Wen
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Li, Yiming
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資訊工程學系
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電信工程研究所
In this paper we propose a silicide design consideration for electrostatic discharge (ESD) protection in nanoscale CMOS devices. According to our practical implementation, it is found that a comprehensive silicide optimization can be achieved on the gate, drain, and source sides with very few testkey designs. Our study shows that there is a high characteristic efficiency for various conditions in particular, for optimizing the performance of sub-100 nm complementary metal-oxide-semiconductor devices in system-on-a-chip era. (c) 2006 Elsevier B.V. All rights reserved.
Analytical solution of nonlinear Poisson equation for symmetric double-gate metal-oxide-semiconductor field effect transistors
(2007-07-01)
Lo, Shih-Ching
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Li, Yiming
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Yu, Shao-Ming
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資訊工程學系
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電信工程研究所
In this paper, an analytical solution of the Poisson equation for double-gate metal-semiconductor-oxide field effect transistor (MOSFET) is presented, where explicit surface potential is derived so that the whole solution is fully analytical. Based on approximations of potential distribution, our solution scheme successfully takes the effect of doping concentration in each region. It provides an accurate description for partially and fully depleted MOSFET devices in different regions of operation. Comparison with numerical data shows that the solution gives good approximations of potential for MOSFETs under different biases and geometry configurations. The solution can be applied to estimate classical and quantum electron density of nanoscale double-gate MOSFETs. (c) 2007 Elsevier Ltd. All rights reserved.
Characteristic fluctuation dependence on discrete dopant for 16nm SOI FinFETs at different temperature
(2007)
Li, Yiming
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Hwang, Chih-Hong
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Yu, Shao-Ming
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Huang, Hsuan-Ming
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Yeh, Ta-Ching
In this paper, we numerically study the discrete-dopant-induced characteristic fluctuations in 16nnn silicon-on-insulator (SOI) FinFETs. For devices under different temperature condition, discrete dopants are statistically generated and positioned into the three-dimensional channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". Electrical characteristics' fluctuations are growing worse when the substrate temperature increases, the standard deviation of threshold voltage increases 1.75 times when substrate temperature increases from 300K to 400K for example. This "atomistic" device simulation technique is computationally cost-effective and provides us an insight into the problem of discrete-dopant-induced fluctuation and the relation between the fluctuation and thermal effect.
Comparison of random-dopant-induced threshold voltage fluctuation in nanoscale single-, double-, and surrounding-gate field-effect transistors
(2006-09-01)
Li, Yiming
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Yu, Shao-Ming
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資訊工程學系
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電信工程研究所
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Department of Computer Science
In this study, we explore random-dopant-induced threshold voltage fluctuation by solving a quantum correction model. Fluctuation of the threshold voltage for three nanoscale transistors, single-, double-, and surrounding-gate (SG, DG, and AG) metal-oxide-semiconductor field-effect transistors (MOSFETs) are computationally compared. To calculate the variance of the threshold voltages of the SG, DG, and AG MOSFETs, a quantum correction model under equilibrium conditions is expanded and numerically solved using perturbation and monotone iterative methods. Fluctuation of the threshold voltage resulting from the random dopant, gate oxide thickness, channel film thickness, gate channel length, and device width are calculated for the three devices. Quantum mechanical and classical results give similar predictions for fluctuation of the threshold voltage with respect to different parameters including the dimensions of the device and the channel doping. Fluctuation increases when the channel doping concentration, channel film thickness, and gate oxide thickness increase, On the other hand, it decreases when the channel length and device width increase. Calculation results of the quantum correction model are quantitatively higher than those of classical estimation in accordance with different quantum confinement effects in nanoscale SG, DG, and AG MOSFETs. It is found that the AG MOSFET has the smallest threshold voltage fluctuation among the three device structures due to its good channel controllability. In contrast to the conventional quantum Monte Carlo approach and the small-signal analysis of the Schrodinger-Poisson equations, this computationally cost-effective quantum correction approach shows acceptable accuracy and is ready for industrial technology computer-aided design application.
Design optimization of a current mirror amplifier integrated circuit using a computational statistics technique
(2008-12-15)
Li, Yiming
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Li, Yih-Lang
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Yu, Shao-Ming
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資訊工程學系
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電信工程研究所
In this work, we implement a Computational statistics technique for design optimization of integrated circuits (ICs). Integration of a well-known circuit simulation software and central composite design method enables us to construct a second-order response surface model (RSM) for each concerned constraint. After Construction of RSMs. we verify the adequacy and accuracy using the normal residual plots and their residual of squares. The constructed models are further employed for design optimization of current mirror amplifier ICs with 0.18 mu m CMOS devices. By considering the voltage gain, cut-off frequency, phase margin, common-mode rejection ratio and slew-rate, six designing parameters including the width and length of different transistors are selected and optimized to fit the targets. (C) 2007 IMACS. Published by Elsevier B.V. All rights reserved.
Discrete dopant fluctuated 20nm/15nm-gate planar CMOS
(2007)
Yang, Fu-Liang
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Hwang, Jiunn-Ren
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Chen, Hung-Ming
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Shen, Jeng-Jung
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Yu, Shao-Ming
We have, for the first time, experimentally quantified random dopant distribution (RDD) induced V-t standard deviation up to 40mV for 20nm-gate planar CMOS. Discrete dopants have been statistically positioned in the 3D channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". As gate length further scaling down to 15nm, the newly developed discrete-dopant scheme features an effective solution to suppress 3-sigma-edge single digit dopants induced V-t variation by gate work function modulation. The extensive study may postpone the scaling limit projected for planar CMOS.
Discrete dopant fluctuations in 20-nm/15-nm-gate planar CMOS
(2008-06-01)
Li, Yiming
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Yu, Shao-Ming
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Hwang, Jiunn-Ren
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Yang, Fu-Liang
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資訊工程學系
We experimentally quantified, for the first time, the random dopant distribution (RDD)-induced threshold voltage (V-t) standard deviation up to 40 mV for 20-nm-gate planar complementary metal-oxide-semiconductor (CMOS) field-effect transistors. Discrete dopants have been statistically positioned in the 3-D channel region to examine the associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation." As the gate length further scales down to 15 nm, the newly developed discrete dopant scheme features an effective solution to suppress the 3-sigma-edge single-digit dopant-induced V-t variation by the gate work function modulation. The results of this paper may postpone the scaling limit projected for planar CMOS.
Discrete Dopant Induced Electrical and Thermal Fluctuation in Nanoscale SOI FinFET
(2007)
Li, Yiming
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Hwang, Chih-Hong
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Yu, Shao-Ming
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Huang, Hsuan-Ming
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電信工程研究所
The International Roadmap for Semiconductors has forecasted a transition from conventional bulk device to silicon-on-insulator (SOI) one, and then to multiple-gate SOI for high-performance devices. Impact of the discrete-dopant number and discrete-dopant position on device characteristics is crucial for nanoscale semiconductor devices. In this paper, the discrete dopant induced electrical and thermal fluctuation of 16nm SOI FinFETs is for the first time explored. A three-dimensional atomistic" device simulation with quantum hydrodynamic equation is proposed and performed for electrical and thermal characteristics of the discrete dopant fluctuated SOI FinFETs. Discrete dopants are statistically positioned in the 3D channel region to study associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". Effect of the discrete-dopant-number- and discrete-dopant-position-induced fluctuations on device characteristic including variations of the lattice and electron temperatures are advanced. The large-scale computational statistics study provides us an insight into the fluctuation of electrical and thermal characteristics and mechanism of immunity against fluctuation in SOI FinFETs.
Electronic design automation using a unified optimization framework
(2008-12-15)
Li, Yiming
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Yu, Shao-Ming
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Li, Yih-Lang
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資訊工程學系
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電信工程研究所
This work proposes an object-oriented unified optimization framework (UOF) for general problem optimization. Based on biological inspired techniques, numerical deterministic methods, and C++ objective design, the UOF itself has significant potential to perform optimization operations on various problems. The UOF provides basic interlaces to define a general problem and generic solver, enabling these two different research fields to be bridged. The components of the UOF can be separated into problem and solver components. These two parts work independently allowing high-level code to be reused, and rapidly adapted to new problems and solvers. The UOF is customized to deal with several optimization problems. The first experiment involves a well-known discrete combinational problem, wihle the second one studies the robustness for the reverse modeling problem, which is in high demanded by device manufacturing companies. Additionally, experiments are undertaken to determine the capability of the proposed methods in both analog and digital circuit design automation. The final experiment designs antenna for rapidly growing wireless communication. Most experiments are categorized as simulation-based optimization tasks in the microelectronics industry. The results confirm that UOF has excellent flexibility and extensibility to solve these problems successfully. The developed open-source project is publicly available. (C) 2007 IMACS. Published by Elsevier B.V. All rights reserved.
Intelligent optical proximity correction using genetic algorithm with model- and rule-based approaches
(2009-03-01)
Li, Yiming
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Yu, Shao-Ming
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Li, Yih-Lang
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資訊工程學系
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電信工程研究所
Optical lithography is one of the key technologies in semiconductor material and device fabrications. It is a process to transfer the layouts of desired pattern onto the wafers. However, the exposure on wafer has distortions due to the proximity effects. As the minimum feature sizes of explored samples continue to shrink, the mismatch between the pattern and the experimental result on wafer is significant. Corrections of mask patterns between the sample and post exposure result are thus necessary. Optical proximity correction (OPC) is the process of modifying the geometries of the layouts to compensate for the non-ideal properties of the lithography process. Given the shapes desired on the wafer, the mask is modified to improve the reproduction of the critical geometry. In this work, we propose an intelligent OPC technique for process distortion compensation of layout mask. To perform the mask correction in sub-wavelength era, two different strategies including the genetic algorithm (GA) with model-based OPC and the GA with rule-based OPC methods are examined. The proposed intelligent system consists of three parts: the preprocess, the OPC engine, and the post-process. During the pre-process, the pattern analyzer will analysis all patterns and then divided them into many segments for model-based OPC or generates assistant patterns for rule-based OPC. Secondly, the OPC module is applied to correct the mask. The intelligent module searches the whole problem domain to find out the best combination of the mask shape by the GA. The corrected mask is verified by performing lithographic simulation to get the error norm between exposed result and desired layout. Finally, the mask verification is conducted in the post-process. By testing on several fundamental patterns, this approach shows good correction accuracy and efficiency, compared with experimentally fabricated samples. It can be applied to perform the mask correction in sub-wavelength era. (C) 2008 Elsevier B.V. All rights reserved.