A quantum hydrodynamic simulation of strained nanoscale VLSI device

Abstract

Strained silicon field effect transistor (FET) has been known for enhancing carrier mobility. The stained Si channel thickness, the Si1-xGex composition fraction and the Si1-xGex layer thickness are three crucial parameters for designing strained Si/SiGe MOSFET. Mobility enhancement and device reliability may be unnecessarily conservative. In this paper, numerical investigation of drain current, gate leakage and threshold voltage for strained Si/SiGe MOSFET are simulated under different device profiles. According to our results, the optimal combination of parameters are as follows: stained Si channel thickness is 7 nm, Ge content is 20%, and the Si1-xGex layer thickness should be chosen between 20 similar to 50 nm.