Browsing by Author "Zous, NK"

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A comparative study of SILC transient characteristics and mechanisms in FN stressed and hot hole stressed tunnel oxides
(1999)
Zous, NK
;
Wang, TH
;
Yeh, CC
;
Tsai, CW
;
Huang, CM
The mechanisms and transient characteristics of hot hole stress and FN stress induced excess leakage currents in tunnel oxides are investigated. Hot hole SILC is found to have a more pronounced transient effect. The transient is attributed to positive oxide charge detrapping and thus annihilation of positive charge-assisted tunneling current. The positive charge assisted tunneling current can be annealed by substrate hot electron injection. The DC and transient components in FN SILC are also discussed.
A comprehensive study of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFET's
(1999-09-01)
Wang, TH
;
Chiang, LP
;
Zous, NK
;
Hsu, CF
;
Huang, LY
The mechanisms and characteristics of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFET's are investigated. Both interface trap and oxide charge effects are analyzed. Various drain leakage current components at zero V-gs such as drain-to-source subthreshold leakage, band-to-band tunneling current, and interface trap-induced leakage are taken into account, The trap-assisted drain leakage mechanisms include charge sequential tunneling current, thermionic-field emission current,:and Shockley-Read-Hall generation current. The dependence of drain leakage current on supply voltage, temperature, and oxide thickness is characterized. Our result shows that the trap-assisted leakage may become a dominant drain leakage mechanism as supply voltage is reduced. In addition, a strong oxide thickness dependence of drain leakage degradation is observed. In ultra-thin gate oxide (30 Angstrom) n-MOSFET's, drain leakage current degradation is attributed mostly to interface trap creation, while in thicker oxide (53 Angstrom) devices, the drain leakage current exhibits two-stage degradation, a power law degradation rate in the initial stage due to interface trap generation, followed by an accelerated degradation rate in the second stage caused by oxide charge creation.
A new technique to measure an oxide trap density in a hot carrier stressed n-MOSFET
(1997)
Wang, TH
;
Chiang, LP
;
Chang, TE
;
Zous, NK
;
Shen, KY
We have proposed a new measurement technique to characterize the hot carrier stress generated oxide traps in a n-MOSFET by measuring subthreshold current. In this technique, a specially designed measurement consisting of a series of oxide charge detrapping and subthreshold current measurement phases was performed. An analytical model accounting for the temporal evolution of subthreshold current due to oxide charge detrapping was derived. Our study shows that this method is extremely sensitive to an oxide charge variation. By using this method, the oxide trap growth rates by hot electron stress and hot hole stress were measured.
A novel erase scheme to suppress overerasure in a scaled 2-bit nitride storage flash memory cell
(2004-09-01)
Yeh, CC
;
Wang, TH
;
Tsai, WJ
;
Lu, TC
;
Liao, YY
The cause of over-erasure in a two-bit nitride storage Flash memory cell is investigated. Extra positive charges accumulated above the n(+) unction and channel-shortening enhanced drain-induced barrier lowering effect are found to be responsible for threshold voltage (V-t) lowering in an over-erased cell. A modified erase scheme is proposed to resolve this issue. By applying a source voltage during erase, the erase speed can be well controlled for cells with different channel lengths and a wide range of program-state Vt distribution, which will reduce overerasure significantly.
A novel fully CMOS process compatible PREM for SOC applications
(2005-03-01)
Yeh, CC
;
Wang, TH
;
Tsai, WJ
;
Lu, TC
;
Liao, YY
A novel nonvolatile memory cell named programmable resistor with eraseless memory (PREM) is proposed for system on chip applications for the first time. PREM combines a novel "eraseless" algorithm and the progressive breakdown of an ultrathin oxide. No or one extra mask is needed with a standard CMOS process. Multitime programming, multilevel cell, nonvolatility, and low-voltage operation are realized. Good reliability is demonstrated based on the result of a single cell.
A novel operation method to avoid overerasure in a scaled trapping-nitride localized charge storage flash memory cell and its application for multilevel programming
(2006-04-01)
Tsai, WJ
;
Zous, NK
;
Wang, TH
;
Ku, YHJ
;
Lu, CY
By using the charge pumping technique, it was found that the injected-hole occupied percentage increases with respect to the whole channel, and overerasure thus happens in a scaled trapping-nitride storage Flash memory cell. Such overerasure can be avoided or can be recovered if the cell is suitably biased during the erase operation. Moreover, the erase threshold voltage can be well controlled by the applied erase gate voltage. The reason is that both the channel-hot electrons and the band-to-band tunneling-induced hot holes would inject at the same time and are in balance as a specific surface potential is achieved. Based on this study, a self-limited soft program, as well as a self-saturated erase scheme, is proposed. Applications of this concept to multilevel programming are also demonstrated.
An endurance evaluation method for flash EEPROM
(2004-05-01)
Zous, NK
;
Chen, YJ
;
Chin, CY
;
Tsai, WJ
;
Lu, TC
Trap generation is hard to estimate in a Flash cell due to a dynamic stress field during program and erase. In this paper, a linear correlation is found between the erase state V-T rollup, and cycling V-T window. With the knowledge of the time dependence of erase stress field based on Fowler-Nordheim (FN) tunneling, the V-T rollup during cycling is evaluated by incorporating field dependent oxide trap generation. The extracted Delta V-T degradation slope during constant FN stress can be applied quantitatively to predict the V-T window closure during Flash cell cycling.
Characterization of various stress-induced oxide traps in MOSFET's by using a novel transient current technique
(1997)
Wang, TH
;
Chiang, LP
;
Zous, NK
;
Chang, TE
;
Huang, C
A new oxide trap characterization technique by employing a two-phase subthreshold current measurement has been developed. By varing the gate bias and the drain bias in measurement, the field and temperature dependences of oxide charge detrapping and the spatial distributions of various stress induced oxide traps are characterized.
Characterization of various stress-induced oxide traps in MOSFET's by using a subthreshold transient current technique
(1998-08-01)
Wang, TH
;
Chiang, LP
;
Zous, NK
;
Chang, TE
;
Huang, C
An oxide trap characterization technique by measuring a subthreshold current transient is developed, This technique consists of two alternating phases, an oxide charge detrapping phase and a subthreshold current measurement phase. An analytical model relating a subthreshold current transient to oxide charge tunnel detrapping is derived. By taking advantage of a large difference between interface trap and oxide trap time-constants, this transient technique allows the characterization of oxide traps separately in the presence of interface traps, Oxide traps created by three different stress methods, channel Fowler-Nordheim (F-N) stress, hot electron stress and hot hole stress, are characterized, By varying the gate bias in the detrapping phase and the drain bias in the measurement phase, the field dependence of oxide charge detrapping and the spatial distribution of oxide traps in the channel direction can be obtained, Our results show that 1) the subthreshold current transient follows a power-law time-dependence at a small charge detrapping field, 2) while the hot hole stress generated oxide traps have a largest density, their spatial distribution in the channel is narrowest as compared to the other two stresses, and 3) the hot hole stress created oxide charges exhibit a shortest effective detrapping time-constant.
Field and temperature effects on oxide charge detrapping in a metal-oxide-semiconductor field effect transistor by measuring a subthreshold current transient
(1997-08-25)
Chiang, LP
;
Zous, NK
;
Wang, TH
;
Chang, TE
;
Shen, KY
A technique to characterize oxide charge detrapping in a Fowler-Nordheim stressed n-metal-oxide-semiconductor field effect transistor is proposed. This technique consist of two alternating phases, an oxide charge detrapping phase and a subthreshold current measurement phase. An analytical model relating a subthreshold current transient to oxide charge density and detrapping time constants was derived. By varying the gate bias in the detrapping phase and the ambient temperature, the field and temperature dependences of oxide charge detrapping can be obtained from the subthreshold current transients measured. (C) 1997 American Institute of Physics.
Investigation of oxide charge trapping and detrapping in a MOSFET by using a GIDL current technique
(1998-07-01)
Wang, TH
;
Chang, TE
;
Chiang, LP
;
Wang, CH
;
Zous, NK
We proposed a new measurement technique to investigate oxide charge trapping and detrapping in a hot carrier stressed n-MOSFET by measuring a GIDL current transient. This measurement technique is based on the concept that in a MOSFET the Si surface field and thus GIDL current vary with oxide trapped charge. By monitoring the temporal evolution of GIDL current, the oxide charge trapping/detrapping characteristics can be obtained. An analytical model accounting for the time-dependence of an oxide charge detrapping induced GIDL current transient was derived, A specially designed measurement consisting of oxide trap creation, oxide trap filling with electrons or holes and oxide charge detrapping was performed. Two hot carrier stress methods, channel hot electron injection and band-to-band tunneling induced hot hole injection, were employed in this work, Both electron detrapping and hole detrapping induced GIDL current transients were observed in the same device. The time-dependence of the transients indicates that oxide charge detrapping is mainly achieved via field enhanced tunneling. In addition, we used this technique to characterize oxide trap growth in the two hot carrier stress conditions. The result reveals that the hot hole stress is about 10(4) times more efficient in trap generation than the hot electron stress in terms of injected charge.
Investigation of oxide charge trapping and detrapping in a n-MOSFET
(1997)
Wang, TH
;
Chang, TE
;
Chiang, LP
;
Zous, NK
;
Huang, C
Oxide hole and electron trapping/detrapping characteristics in a hot carrier stressed n-MOSFET were investigated by monitoring the temporal evolution of band-to-band tunneling current. Both the hole and electron detrapping induced GIDL current transients were observed for the first time in the same device. The obtained field dependence of oxide charge detrapping time indicates that trapezoidal barrier tunneling is a major mechanism in both hole and electron detrapping. A trap assisted sequential tunneling model for hole detrapping was used to match the measured trap time constants.
Investigation of programmed charge lateral spread in a two-bit storage nitride flash memory cell by using a charge pumping technique
(2004)
Gu, SH
;
Wang, MT
;
Chan, CT
;
Zous, NK
;
Yeh, CC
The lateral distribution of programmed charge in a hot electron program/hot hole erase nitride storage flash cell is investigated by using a charge pumping technique. Our study shows that the secondly programmed bit has a wider trapped charge distribution than the first programmed bit. In addition, we find prograrnmed charge spreads further into the channel with program/erase cycle number.
Lateral migration of trapped holes in a nitride storage flash memory cell and its qualification methodology
(2004-09-01)
Zous, NK
;
Lee, MY
;
Tsai, WJ
;
Kuo, A
;
Huang, LT
The negative threshold voltage (V-t) shift of a nitride storage flash memory cell in the erase state will result in an increase in leakage current. By utilizing a charge pumping method, we found that trapped hole lateral migration is responsible for this V-t shift. Hole transport in nitride is characterized by monitoring gate induced drain leakage current and using a thermionic emission model. The hole emission induced V-t shift shows a linear correlation with bake time in a semi-logarithm plot and its slope depends on the bake temperature. Based on the result, an accelerated qualification method for the negative V-t drift is proposed.
Positive oxide charge-enhanced read disturb in a localized trapping storage flash memory cell
(2004-03-01)
Tsai, WJ
;
Yeh, CC
;
Zous, NK
;
Liu, CC
;
Cho, SK
Read disturb-induced erase-state threshold voltage instability in a localized trapping storage Flash memory cell with a poly-silicon-oxide-nitride-oxide-silicon (SONOS) structure is investigated and reported. Our results show that positive trapped charge in bottom oxide generated during program/erase (P/E) cycles play a major role. Both gate voltage and drain voltage will accelerate the threshold voltage (V-t) drift. Hot-carrier caused disturb effect is more severe in a shorter gate length device at low temperature. A model of positive charge-assisted electron tunneling into a trapping nitride is proposed. Influence of channel doping on the V-t drift is studied. As the cell is in an "unbiased" storage mode, tunnel detrapping of positive oxide charges is responsible for the threshold voltage shift, which is insensitive to temperature.
Role of positive trapped charge in stress-induced leakage current for flash EEPROM devices
(2002-11-01)
Wang, TH
;
Zous, NK
;
Yeh, CC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The transient behavior of hot hole (HH) stress-induced leakage current (SILC) in tunnel oxides is investigated. The dominant SILC mechanism is positive oxide charge-assisted tunneling (PCAT). The transient effect of SILC is attributed to positive oxide charge detrapping and thus the reduction of PCAT current. A correlation between SILC and stress-induced substrate current is observed. Our study shows that both SILC and stress-induced substrate current have power law time-dependence t(-n) with the power factor n about 0.7 and 1, respectively. Numerical analysis for PCAT current incorporating a trapped charge caused Coulombic potential in the tunneling barrier is performed to evaluate the time-and field-dependence of SILC and the substrate current. Based on our model, the evolution of threshold voltage shift with read-disturb time in a Flash EEPROM cell is derived. Finally, the dependence of SILC on oxide thickness is explored. As oxide thickness reduces from 100 Angstrom to 53 Angstrom, the dominant SILC mechanism is found to change from PCAT to neutral trap-assisted tunneling (TAT).
Temperature effect on read current in a two-bit nitride-based trapping storage flash EEPROM cell
(2004-07-01)
Liu, MY
;
Chang, YW
;
Zous, NK
;
Yang, I
;
Lu, TC
The temperature effect on the read current of a two-bit nitride-storage Flash memory cell is investigated. In contrast to a conventional silicon-oxide-nitride-oxide (SONOS) cell with uniform Fowler-Nordheim (FN) programming, a significant high-V-T state read current increase, which results in the read window narrowing at high temperature, is observed in a channel hot electron (CHE) programmed cell. The increment of high-V-T state leakage current shows a positive correlation with program/erase threshold voltage window. Since the temperature effect is very sensitive to a locally trapped charge profile, a two-dimensional simulation with a step charge profile is employed to characterize the relationship between current increment and both charge width and charge density.
Transient effects of positive oxide charge on stress-induced leakage current in tunnel oxides
(1999-08-02)
Zous, NK
;
Wang, TH
;
Yeh, CC
;
Tsai, CW
;
Huang, CM
The role of positive oxide charge in excess low-level leakage current in tunnel oxides induced by Fowler/Nordheim stress is investigated. A correlation between stress-induced gate current and substrate current in an n-channel metal-oxide-semiconductor field-effect transistor is observed. Both the gate current and the substrate current exhibit a significant transient effect. The mechanisms of the stress-induced currents and their field dependence are explored. Positive oxide charge tunnel detrapping is found to be the cause of the observed transient behavior in the two currents. The stress-created positive oxide charge can be significantly annealed by substrate hot electron injection. (C) 1999 American Institute of Physics. [S0003-6951(99)02226-3].
Voltage scaling and temperature effects on drain leakage current degradation in a hot carrier stressed n-MOSFET
(1998)
Wang, TH
;
Hsu, CF
;
Chiang, LP
;
Zous, NK
;
Chao, TS
Drain leakage current degradation at zero V-gs in a hot carrier stressed n-MOSFET is measured and modeled. The dependences of drain leakage current on supply voltage and temperature are characterized. In modeling, various drain leakage current mechanisms including drain-to-source subthreshold leakage current, band-to-band tunneling current and interface trap assisted leakage current are taken into account. Our result shows that interface trap induced leakage current appears to be a dominant drain leakage mechanism as the supply voltage is scaled below 3.0V. Drain leakage current degradation by orders of magnitude has been observed due to hot carrier stress.