Browsing by Issue Date, starting with "1993-04-01"

Now showing 1 - 20 of 89703

FORMATION OF EXCELLENT SHALLOW N+P JUNCTIONS BY AS+ IMPLANTATION INTO THIN COSI FILMS ON SI SUBSTRATE
(1993-04-01)
LIN, CT
;
JUANG, MH
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CHU, CH
;
CHENG, HC
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電子工程學系及電子研究所
Excellent shallow n + p junctions with a leakage current density of about 0.6 nA/cm2 have been fabricated by As+ implantation into thin CoSi films on Si substrates and subsequent drive-in/silicidation. The resultant junction characteristics are strongly affected by the implant conditions. A deeper as-implanted dopant profile is more helpful to drive the dopant within the silicides into the junction regions. Because the silicidation facilitates damage annihilation, the implant conditions forming excellent junctions in this scheme own large process window and thus yield low thermal budgets. Rapid thermal annealing was not favorable to forming junctions in this scheme because of its short annealing times for the arsenic drive-in.
INTERFACIAL REACTIONS OF TITANIUM THIN-FILMS ON ION-IMPLANTED (001) SI
(1993-04-01)
LIAUH, HR
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CHEN, MC
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CHEN, JF
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CHEN, LJ
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LUR, W
An investigation on the influences of doping impurities on the formation of titanium silicide has been carried out. The formation of polycrystalline silicide was observed to be retarded by the presence of As in Ti/As+-Si samples compared with those in Ti/BF2+-Si samples. Superior thermal stability of TiSi2 was found to occur in BF2+ implanted samples than that in blank and As+ implanted samples. The resistance to island formation in BF2+ implanted samples is attributed to the retardation of grain growth by the segregation of fluorine atoms at the grain boundaries.
A NEW METRIC FOR OBJECT-ORIENTED DESIGN
(1993-04-01)
CHEN, JY
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LU, JF
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交大名義發表
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資訊工程學系
;
National Chiao Tung University
The paper presents a new metric for the object-oriented design. The metric measures the complexity of a class in an object-oriented design. The metrics include operation complexity, operation argument complexity, attribute complexity, operation coupling, class coupling, cohesion, class hierarchy, and reuse. An experiment is conducted to build the metric system. The approach is to derive a regression model of the metrics based on the experimental data. Moreover, the subjective judgement by the expert is incorporated in the regression model. This ensures that the metric system is pragmatic and flexible for the software industry.
STABILIZATION, PARAMETERIZATION, AND DECOUPLING CONTROLLER-DESIGN FOR LINEAR-MULTIVARIABLE SYSTEMS
(1993-04-01)
LIN, CA
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HSIEH, TF
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電控工程研究所
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Institute of Electrical and Control Engineering
We study linear multivariable systems under the unity-feedback configuration. For nonsquare plants with no coincidences of unstable poles and zeros, we prove a simplified condition for closed-loop stability. The simplification leads to a simple description of the set of all achievable I / O maps and a simple parameterization of all controllers achieving the same I / O map. The results are used to describe the set of all achievable decoupled I / O maps and prove a necessary and sufficient condition for the existence of stable decoupling controllers.
NOVEL ALGAAS/GAAS HETEROJUNCTION BIPOLAR-TRANSISTORS FABRICATED BY 2-STAGE MOLECULAR-BEAM EPITAXY
(1993-04-01)
CHEN, HR
;
CHANG, CY
;
TSAI, KL
;
TSANG, JS
;
LEE, CP
Two-stage molecular beam epitaxy (MBE) growth was employed to fabricate AlGaAs/GaAs heterojunction bipolar transistors (HBTs) for the first time. Due to the unique base contact layer design, the base can be made very thin without increasing the extrinsic base sheet resistance and the etching of the base contact can be done very easily and very reliably. In addition, the base-collector separation layer design contributed to the reduction of parasitic capacitance. D.C. differential current gains up to 110 and 200 were obtained for 1000 and 500 angstrom base width, respectively.
UNIVERSAL PRINCIPAL AXES - AN EASY-TO-CONSTRUCT TOOL USEFUL IN DEFINING SHAPE ORIENTATIONS FOR ALMOST EVERY KIND OF SHAPE
(1993-04-01)
LIN, JC
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交大名義發表
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資訊工程學系
;
National Chiao Tung University
;
Department of Computer Science
A convenient tool for defining shape orientations called universal principal axes is introduced. These axes are formed of half lines starting from the shape centroid, with their directional angles expressed as functions of the polar angle of the first non-zero complex number encountered in the sequence integral integral(x + iy)l dA with l = 2, 3, 4,..., provided that the integration domain is taken to be the given two-dimensional (2D) shape and the origin is assumed to be the shape centroid. Universal principal axes are shown to be independent of the translation, scaling, and rotation of the coordinate system used, and they are therefore qualified in defining shape orientations. A major benefit of using the proposed universal principal axes is that they exist for almost every kind of shape. Another benefit is that there is no need to judge in advance whether a given shape is mirror-symmetric, rotationally symmetric, irregular, etc. Moreover, in the case of rotationally symmetric shapes, the universal principal axes make the preprocessing procedure for detecting the number of folds contained in the given shape unnecessary although such procedure is essential for many existing tools designed to define orientations of rotationally symmetric shapes. Defining shape orientations by universal principal axes is therefore quite convenient. An algorithm describing the construction of universal principal axes and several examples showing the detected universal principal axes for some shapes of distinct types are given. The relationship between universal and conventional principal axes is also discussed.
A UNIFIED 3-D MOBILITY MODEL FOR THE SIMULATION OF SUBMICRON MOS DEVICES
(1993-04-01)
YANG, JJ
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CHUNG, SSS
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CHANG, CH
;
LEE, GH
;
電子工程學系及電子研究所
A calibrated and physically based mobility model is developed for three-dimensional simulation of submicron metal-oxide-semiconductor (MOS) devices, in which the inversion layer mobility is emphasized. This inversion layer mobility can be generalized into a local form, i.e., expressed as functions of the local electric field at each grid point, so that it is well suited for device simulation. The resulting 3-D mobility model accurately characterizes the significant physical scattering effects including the Coulomb screening effect, quantum channel broadening effect, surface roughness scattering, structure-induced lateral surface scattering and velocity saturation limited effects. Results show that this new model can be incorporated into device simulators for accurately predicting drain currents of submicron LDD MOS devices. Moreover, the results compare more favorably with the experimental data than do those for other reported models.
OPTIMIZED INTEGRATED CMOS OPTICAL RECEIVER FOR OPTICAL INTERCONNECTS
(1993-04-01)
HUANG, YT
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The optimisation of an optical receiver is discussed and transient charcteristics of two basic simple integrated receivers in CMOS systems are analysed and compared in detail. In analysis, a maximum current parameter is developed and used for optimisation design. Among these two receivers, the low-impedance configuration is presented for high-speed operation. SPICE simulation and preliminary experimental results with discrete devices are also illustrated and discussed.
SYNTHESIS AND CHARACTERIZATION OF BLOCK COPOLYMERS OF POLYETHER SULFONE WITH LIQUID-CRYSTALLINE POLYESTERS
(1993-04-01)
HSU, CS
;
CHEN, LB
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交大名義發表
;
應用化學系
;
National Chiao Tung University
A series of novel ABA block copolymers containing a liquid crystalline polyester (A) block and an amorphous polyether sulfone (B) block were prepared. The block copolymers were characterized by FT-IR spectroscopy, differential scanning calorimetry, thermogravimetric analysis, optical polarizing microscopy and X-ray diffraction measurement. Calculated results obtained from FT-IR spectra and a hydrolysis study reveal that the block copolymers contain 17-33% weight of polyether sulfone segments. All the prepared block copolymers have shown a liquid crystalline property. The block copolymer containing 33% polyether sulfone presented a glass transition at 180-degrees-C and a crystalline to nematic phase transition at 278-degrees-C. The other copolymers have exhibited only a crystalline to nematic phase transition at approximately 255-degrees-C.
THEORY OF SELF-INDUCED TRANSPARENCY IN A KERR HOST MEDIUM BEYOND THE SLOWLY-VARYING-ENVELOPE APPROXIMATION
(1993-04-01)
CHI, SE
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WANG, TY
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WEN, SF
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電信研究中心
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光電工程研究所
The self-induced transparency in the Kerr host medium has been studied beyond the slowly-varying-envelope approximation. An analytic solution is obtained. There exists a hyperbolic-secant soliton whose power, pulse width, group velocity, and propagation constant are uniquely determined for given parameters of the medium. The reductions of the group velocities of the solitons by the self-induced-transparency effect in the resonant medium with homogeneous and inhomogeneous broadening are also studied. It is found that there is negative dispersion induced by the self-induced transparency, which is not predicted by the theory with the slowly-varying-envelope approximation. The amount of the induced dispersion is determined by the total dispersion of the system required to be compensated by the Kerr effect. Numerical examples of the self-induced transparency in an erbium-doped fiber are shown. In a typical erbium-doped fiber, the soliton solution has not been found because the inhomogeneous-broadening linewidth of the medium is too large.
SOLVENT-MEDIATED IODINE INTERCALATION OF A HIGH-TC OXIDE SUPERCONDUCTOR BI2SR1.8CA1.2CU2OX
(1993-04-01)
GUO, TN
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CHEN, TM
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交大名義發表
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應用化學系
;
National Chiao Tung University
The benzene-mediated iodine intercalation into the pseudo-layered superconductor Bi2Sr1.8Ca1.2Cu2Ox (2212) is an efficient way to prepare an intercalate with nominal composition IBi2Sr1.8Ca1.2Cu2Ox. Expansion by 22 percent along the crystallographic c-axis was observed but both a-and b-axes of the intercalates remained unchanged. The superconducting temperature (T(c)) of 2212 phase decreased 10 K upon iodine intercalation. We report the first solvent-mediated intercalation reaction and preliminary characterizations of a presumably stage-1 phase IBi2Sr1.8Ca1.2Cu2Ox.
DIELECTRIC DEGRADATION OF PT/SIO2/SI STRUCTURES DURING THERMAL ANNEALING
(1993-04-01)
TSUI, BY
;
CHEN, MC
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Traditionally it was believed that platinum does not interact with silicon dioxide during thermal treatment in an N2 ambient. In this work, however, dielectric degradation of the Pt/SiO2/Si structure during thermal annealing was observed. The density of surface states at the SiO2/Si interface increases and the dielectric strength of the oxide decreases after annealing at temperatures higher than 600-degrees-C. Ion implantation through the Pt/SiO2 structure enhances the degradation. After removal of the Pt film, a second annealing can reduce the surface state density but the dielectric strength cannot be recovered. Although material analysis such as AES and SIMS shows no obvious differences between the fresh SiO2 and the degraded SiO2, electrical analyses indicate that thermal stress is responsible for the increase of the surface states while Pt dissolving in SiO2 is responsible for the decrease of the dielectric strength. Thus, the process sequence should be taken into consideration for practical application.
NUMERICAL-SIMULATION OF SIDEGATING EFFECT IN GAAS-MESFETS
(1993-04-01)
CHANG, SJ
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LEE, CP
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Two-dimensional simulation of the sidegating effect in GaAs MESFET's has been performed. The result confirms that Schottky contacts on a semi-insulating substrate cause serious high substrate leakage current and drain current reduction in GaAs MESFET's. The threshold behavior in sidegating effect is found to correlate with the conduction behavior of the Schottky-i-n(sidegate) structure when the sidegate is negatively biased. Shielding and enhancement of the sidegating effect by the Schottky contacts have also been studied and the results agree with the experimental findings. Besides, the presence of hole traps in the semi-insulating substrate is found to be essential to the sidegating effect.
LINEAR DEPENDENCY CHECK IN BUILT-IN TEST
(1993-04-01)
YANG, C
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資訊管理與財務金融系註：原資管所+財金所
;
Department of Information Management and Finance
Given a characteristic polynomial p(x) and a sampling polynomial with respect to p(x), a designer likes to know whether the sampling polynomial is a dependency polynomial. A dependency polynomial gives low fault coverage in the built-in self test. The tool LDC computes the residue combinations of the factors in the set polynomial and advises designers if the sampling polynomial covers all the testing space. When the sampling polynomial is a dependency polynomial, LDC will try to find one, if any, independent polynomial at a minimum cost. In cases of short test vectors LDC can exhaustively enumerate all independent polynomials for the designers to choose from. This paper reviews the basics of the linear dependency computation, explains the LDC capabilities and its usefulness, and discusses the computational issues of the problem.
CRYPTOSYSTEM FOR SELECTIVELY BROADCASTING SEPARATE SECRETS
(1993-04-01)
WU, TC
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YEH, YS
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資訊科學與工程研究所
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Institute of Computer Science and Engineering
SEESIM - A FAST SYNCHRONOUS SEQUENTIAL-CIRCUIT FAULT SIMULATOR WITH SINGLE-EVENT EQUIVALENCE
(1993-04-01)
WU, CP
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LEE, CL
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SHEN, WZ
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The paper presents a concept of single event equivalence to be used in the sequential circuit fault simulator. The concept dynamically identifies the equivalent faults for a simulated pattern. It combines advantages of the fanout-free region, critical path tracing and the dominator concept, which were applicable only to combinational circuit fault simulation. The implemented fault simulator, SEESIM, based on the concept, demonstrated a performance superior to that of a state-of-the-art concurrent fault simulator, and comparable to that of parallel-pattern single-fault propagation simulators. It requires a minimal amount of memory and, because of its simplicity, can be easily extended to multilogic or higher level simulation.
ENHANCED O2 PLASMA STRIPPING OF P+ AND SI+ IMPLANTED NEGATIVE RESIST BY H2 PLASMA PRETREATMENT
(1993-04-01)
LOONG, WA
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YEN, MS
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WANG, FC
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HSU, BY
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LIU, YL
Hydrogen plasma pretreatments (100 W, 20 sccm, 0.2 torr, 40 approximately 115-degrees-C, 10 approximately 30 min) of Si+, P+, B+ and As+ implanted (100 keV, 1x10(15) ion/cm2) Hunt HR-200 negative resists to the oxygen plasma stripping (100 W, 40 sccm, 0.45 torr, 40 approximately 115-degrees-C) were studied in this report. The results showed that only the resistance to oxygen plasma stripping of Si+ and P+ implanted HR-200 were greatly reduced at the conditions in this study. The activation energies Eact of Si+ and P+ implanted HR-200 by oxygen plasma stripping can be both brought down from approximately 1.3 to approximately 0.85 kcal/mole by hydrogen plasma pretreatment. The FTIR, SEM and ESCA analyses indicated the decreasing of carbonization layers by hydrogen plasma pretreatments.
A STUDY OF LATCH-UP HYSTERESIS IN N-WELL CMOS BY MEANS OF I-V-CHARACTERISTICS AND PHOTOEMISSION TECHNIQUES
(1993-04-01)
CHEN, MJ
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JENG, JK
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Characterization of latch-up by I-V characteristics as well as by the photoemission technique has been extensively performed on a specially-designed CMOS p-n-p-n structure, furnishing different contact combinations for producing the hysteresis phenomenon of latch-up I-V characteristics. Based on these results, we have concluded that the parasitic lateral resistance of the p+ emitter in the n-well is the dominant factor in the formation of the I-V hysteresis. One example in the simplest contact combination has been presented to demonstrate this conclusion. In this example of hysteresis of the latch-up I-V curve, two active latch-up paths have been located separately using the photoemission technique and thus the corresponding branches of I-V curve have been determined. One latch-up path corresponding to the lower I-V branch has been verified to have the lateral p+ emitter resistance in series. The value of such resistance has been extracted by experimentally reproducing the lower I-V curve and has been shown to agree closely with that obtained independently from the p+ emitter. The hysteresis phenomenon in the latch-up I-V characteristics has been found to disappear after decreasing critically or eliminating this resistance by making the remaining p+ emitter contacts partially or totally connected to the power supply. A latch-up equivalent circuit drawn from the experimental results have been proposed to reasonably interpret the anomalous observations.
REALTIME 3D SIMULATION OF 3-AXIS MILLING USING ISOMETRIC PROJECTION
(1993-04-01)
HSU, PL
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YANG, WT
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交大名義發表
;
電控工程研究所
;
National Chiao Tung University
The paper presents an efficient realtime simulator for 3-axis milling processes. In this system, solid modeling is performed using isometric projection with a z-map structure. As a result, all the solid elements are either fully exposed or fully hidden, and they are well arranged and symmetrical. These characteristics make visible surface determination for the raster display more efficient, and they reduce the memory requirements considerably. As a result, this efficient and realtime voxel-based model can simulate NC milling processes satisfactorily even in personal computers, without the aid of extra hardware devices or coprocessors. This simulation system will be useful to NC programmers and machining operators for identifying programs and checking gross programming errors visually.
RESTRUCTURING AND LOGIC MINIMIZATION FOR TESTABLE PLA
(1993-04-01)
HWANG, GH
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SHEN, WZ
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Based on the testable design techniques proposed in [12], [13], we first derive a testability measure named UCP (Untestability Cube-number Product) which can accurately indicate the extra logic needed in testable PLA. Using UCP as a cost function, we have developed two new algorithms. The first one is a restructuring algorithm named REST, and the other is a logic minimizer for testable PLA named LMTPLA. REST can not only restructure a minimized PLA and improve its UCP, but also preserve the same logic function and almost the same chip area simultaneously. Thus, we can make the restructured PLA testable by taking less extra hardware. In order to get a minimum UCP, two new techniques are proposed: 1) Cube-Reduction, and 2) Cube-Partition. Using Cube-Reduction, we can make cubes far from the primes and increases the testability. By Cube-Partition, we may find out those hard-to-test cubes and partition them into smaller but easier-to-test cubes. LMTPLA is principally based on ESPRESSO-II and REST. Different from other logic minimizers, it can consider the testability at the logic minimization process. In order to minimize UCP as well as the number of product terms, four strategies are developed: 1) deleting the cubes with poor testability and reserving the cubes with good testability, 2) giving up the primes, 3) if necessary, partitioning the more untestable cubes into smaller cubes, and 4) deleting the procedures which are useless in LMTPLA. REST and LMTPLA have been implemented on SUN4/260 in C language. For 40 benchmark circuits, the hardware overheads required are reduced by about 30-40%.