Browsing by Issue Date, starting with "1994-09-26"

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FABRICATION OF P-CHANNEL POLYCRYSTALLINE SI1-XGEX THIN-FILM TRANSISTORS BY ULTRAHIGH-VACUUM CHEMICAL-VAPOR-DEPOSITION
(1994-09-26)
LIN, HC
;
JUNG, TG
;
LIN, HY
;
CHANG, CY
;
CHEN, LP
In this report, we present a novel approach for fabricating polycrystalline silicon-germanium thin-film transistors at low temperatures (less than or equal to 550 degrees C). A bottom gate configuration is used for this approach, and an i-Si1-xGex/i-Si/p(+)-Si1-yGey multilayer is deposited sequentially on the gate oxide using an ultra-high vacuum chemical vapor deposition technique. The i-Si1-xGex serves as the channel while the i-Si is used as a buffer layer for allowing p(+)-Si1-yGey to be etched selectively on. p-channel thin-film transistors with a held-effect mobility of 13 cm(2)/V s were achieved using this method, which is superior to those grown by low pressure chemical vapor deposition. Our results indicate that the deposition of poly-Si1-xGex/poly-Si multilayer structure would be a promising way for polycrystalline thin-film device applications.
INFLUENCE OF THERMODYNAMIC FACTORS ON GROWTH OF ALAS1-XSBX ALLOYS
(1994-10-01)
CHEN, WK
;
CHIN, MT
;
交大名義發表
;
電子物理學系
;
National Chiao Tung University
Epitaxial layers of AlAs1-xSbx have been prepared by metalorganic vapor phase deposition (MOCVD) in a horizontal, atmospheric-pressure quartz reactor. The influences of the V/III ratio and the input partial pressure of trimethylantimony were systematically studied. The experimental results are in good agreement with the calculated ones, based on thermodynamic considerations, which implies that the growth of AlAsSb in MOCVD is controlled predominantly by thermodynamics.
THERMAL-STABILITY OF CU/COSI2 CONTACTED P+N SHALLOW JUNCTION WITH AND WITHOUT TIW DIFFUSION BARRIER
(1994-10-01)
CHIOU, JC
;
CHEN, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The thermal stability of Cu/CoSi2 contacted p+n shallow junction diodes with and without TiW diffusion barrier was investigated with respect to metallurgical reaction and electrical characteristics. Without the diffusion barrier, the Cu (2000 angstrom)/CoSi2 (700 angstrom)/p+n diodes (with a junction depth of 0.2 mum measured from the silicide surface) were able to sustain a 30 s rapid thermal annealing (RTA) in N2 ambient up to 450-degrees-C without losing the integrity of the devices characteristics. The Cu3Si phase was observed at the CoSi2/Si interface after 500-degrees-C annealing; the phase penetrated through the CoSi2 layer causing a catastrophic change in layer structure after 700-degrees-C annealing. With the addition of a 1200 angstrom thickness of TiW diffusion barrier between Cu and CoSi2, the junction diodes were able to sustain the RTA treatment up to 775-degrees-C without degrading the basic electrical characteristics, and no metallurgical reaction could be observed even after an 800-degrees-C annealing.
THE COMBINED EFFECTS OF LOW-PRESSURE NH3-ANNEALING AND H-2 PLASMA HYDROGENATION ON POLYSILICON THIN-FILM TRANSISTORS
(1994-10-01)
YANG, CK
;
LEI, TF
;
LEE, CL
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The low pressure NH3-annealing and the H-2. plasma hydrogenation were jointly used to improve the characteristics of polysilicon thin-film transistors (TFT's). It was found that the TFT's after applying the above treatments achieved better subthreshold swings, threshold voltages, field effect mobilities, off currents, and reliability. It is believed that the improvement was due to the gate oxynitride formation and the H-2-plasma had a better passivation effect on the oxynitride.
AUTOMATIC FORM FEATURE RECOGNITION AND 3D PART RECONSTRUCTION FROM 2D CAD DATA
(1994-10-01)
LIU, CH
;
PERNG, DB
;
CHENZ
;
資訊科學與工程研究所
;
工業工程與管理學系
In this paper, a method which can recognize form features and reconstruct 3D part from 2D CAD data automatically is proposed. First, we use the divide-and-conquer strategy to extract the vertex-edge data from each 2D engineering drawing of IGES format. Then, a set of production rules are developed to facilitate the form feature matching process. A new structure of form feature adjacency graph (FFAG) is devised to record the related attributes of each form feature. Finally, to avoid the combinatorial subparts-composition problem, a sweeping operation and volumetric intersection approach is used to rapidly reconstruct the remaining 3D object. The last reconstructed 3D object is used as the base of the FFAG. All the recognized form features in the FFAG can be classified as depression or protrusion features on the 3D part base. The FFAG structure can be easily transformed into CSG/DSG structure, which is readily integrated with the downstream CAPP/CAM systems. A detailed example is provided to illustrate the feasibility and effectiveness of the proposed system.
GROWTH, SELF-RANDOMIZATION, AND PROPAGATION IN A LORENTZ LATTICE-GAS
(1994-10-01)
MENG, HF
;
COHEN, EGD
;
物理研究所
;
Institute of Physics
A systematic study is carried out of a Lorentz lattice gas in order to model the growth dynamics of order-disorder interfaces. In the model, a particle, initially at the origin, moves on the bonds of an initially ordered square lattice, with sites covered by periodically repeated square blocks of 1, 4, or 9 right or left scattering rotators, whose orientations change after collisions with the particle. Depending then on the initial conditions of the blocks and the particle, one observes the following: (a) the particle randomizes the rotator orientations completely, in an ever growing disordered ''liquid'' phase inside the ordered ''solid'' phase on the rest of the lattice; (b) the particle propagates suddenly after a transient randomization period as in (a); or (c) the particle propagates through the ordered lattice immediately. A simple picture for the growth of the randomized region, which proceeds via an interface of fractal dimension 0.75, is discussed. The nature of the propagation for the cases mentioned can be modified by collisions with impurities.
WDM CODING SYSTEM WITH SINGLE PARITY-CHECK CHANNEL
(1994-10-01)
KAO, MS
;
SHAO, SK
;
CHEN, HY
;
電信工程研究所
;
電信研究中心
We propose a modified WDM coding system with a single parity-check channel to achieve an efficient and flexible WDM coding system. The system provides most of the advantages of the original WDM coding system with just one parity-check channel. The bit rate and the data sequences are unaffected by the coding processes, making it very attractive for practical lightwave systems with standard rates. Compared to serial coding systems, it is able to reduce the number of encoding/decoding pairs in an m-channel WDM transmission system operated at STS-N from m x N to one. We have evaluated the system performance and analyzed the performance of frame synchronization needed for the modified WDM coding system. An example shows that the WDM coding can reduce the error floor of a four-channel dispersion-limited WDM system from 10(-10) to 10(-19) with reliable frame synchronization.
FAST SEQUENTIAL-DECODING ALGORITHM-BASED ON DYNAMIC SEARCHING STRATEGY
(1994-10-01)
LEE, CY
;
YANG, WW
;
JENG, LF
;
交大名義發表
;
電子工程學系及電子研究所
The authors present a new sequential decoding algorithm based on dynamic searching strategy to improve decoding efficiency. The searching strategy is to exploit both 'sorting' and 'path recording' techniques. By means of sorting, it is possible to identify the correct path in a very fast way and then, by the recording, the bit sequence can be recovered without degrading decoding performance. The authors also develop a conditional resetting scheme to overcome the buffer overflow problem encountered in conventional sequential decoding algorithms. Simulation results show that, for a given code, the decoding efficiency remains the same as that obtained from maximum likelihood function by appropriately selecting sorting length and decoding depth. In addition, this algorithm can easily be mapped onto an area-efficient VLSI architecture to implement long constraint length convolutional decoders for high-speed digital communications.
STUDIES OF ELECTRON-HYDROGEN ATOM COLLISION BY EIKONAL APPROXIMATION
(1994-10-01)
CHUU, DS
;
HUNG, HC
;
LEE, YC
;
物理研究所
;
Institute of Physics
The eikonal approximation is applied to study the elastic and inelastic scattering of an electron by the hydrogen atom. The trajectory of the incident electron is assumed as a hyperbolic curve. 1s - 1s, 1s - 2s and 1s - 2p differential cross sections at various incident electron energies are calculated and compared with the previous works. Our calculated differential cross sections agree better with the corresponding observed values than those obtained by the first order Born approximation and straight line or angle eikonal approximations, especially in the larger scattering angle region. It is also found that the exchange effect for the incident and the atomic electrons becomes important as the incident energy is below similar to 50 eVs. The including of the exchange effect at low energy indeed improves the calculated results. It is found that hyperbolic eikonal approximation is superior to the straight line or angle eikonal approximation in the incident electron energy range of 50 similar to 200 eVs.
AN ADA-LIKE SOFTWARE PROCESS LANGUAGE
(1994-10-01)
CHEN, JY
;
TU, CM
;
資訊工程學系
;
Department of Computer Science
This article presents a new software process language called concurrent software process language (CSPL). CSPL demonstrates a unique approach in combining the Ada-like syntax with UNIX shell semantics within a software process language. The rich Ada constructs allow CSPL to model the complexity in software processes. Meanwhile, the UNIX shell provides process enaction and, more importantly, easy access to powerful UNIX tools. A CSPL prototype has been built on the Sun workstation. Examples illustrate how CSPL can be used to model objects, activities, events, generics, exceptions, etc., in software processes. Moreover, a meta-process is given to depict a process of developing CSPL process programs. Related work and a preliminary evaluation of CSPL are also depicted.
MEASURING 3-D LOCATION AND SHAPE-PARAMETERS OF CYLINDERS BY A SPATIAL ENCODING TECHNIQUES
(1994-10-01)
CHEN, Z
;
CHIA, TL
;
HO, SY
;
交大名義發表
;
資訊科學與工程研究所
We are concerned with the problem of estimation of true cylinder radius, height, location, and orientation. We present mathematical models for measuring these location and shape parameters using a spatial encoding technique. A crucial step in the proposed method is to convert the estimation problem with complex curved stripe patterns to an equivalent, but simpler, estimation problem with line stripe patterns. The notions of silhouette edges and virtual plane are introduced. Various projective geometry techniques are applied to derive the cylinder location and shape parameters. The actual experiment apparatus is set up to employ the developed mathematical models to measure the cylinder geometric parameters. Description of the image-processing tasks for extracting perceived curved stripes and stripe endpoints is given. Sensitivity analysis and proper measures are taken to consider the effects of the uncertainties of stripe endpoints and silhouette edge locations on the measurement. Experiments have confirmed that our measurement method yields quite good results for different cylinders under various measurement environment conditions.
INVESTIGATION OF NEGATIVE DIFFERENTIAL RESISTANCE PHENOMENA IN GASB/ALSB/INAS/GASB/ALSB/INAS STRUCTURES
(1994-10-01)
WANG, YH
;
LIU, MH
;
HOUNG, MP
;
CHEN, JF
;
CHO, AY
The negative differential resistance (NDR) phenomena were observed in GaSb/AlSb/InAs/-GaSb/AlSb/InAs resonant interband tunnel structures. Electron has resonantly achieved interband tunneling through the InAs/GaSb broken-gap quantum well. The InAs well width causes significant variations of the peak current density and NDR behaviors. The peak current density varies exponentially with the AlSb barrier thickness. The multiple NDR behavior was observed with appropriate InAs well and AlSb barrier thickness, e.g., 30 angstrom thick AlSb barrier and 240 angstrom wide InAs well. Only single negative resistance has, otherwise, been seen. The three-band model was used to interpret the effect of the InAs well and AlSb barrier on the current-voltage characteristics of GaSb/AlSb/InAs/GaSb/AlSb/InAs structures.
A PARALLEL BIT-LEVEL MAXIMUM MINIMUM SELECTOR TO DIGITAL AND VIDEO SIGNAL-PROCESSING
(1994-10-01)
LEE, CY
;
JUAN, SC
;
YANG, WW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a novel circuit for parallel bit-level maximum/minimum selection. The selection is based on a label-updating scheme which sequentially scans a set of data patterns from MSB to LSB and generates corresponding labels. The complete circuit realizing this scheme consists of a set of updating units and a global OR unit, where each updating unit is composed of only a few basic gates. Due to structure modularity, the developed circuit provides a very cost-effective hardware solution for comparing large volumes of data patterns as those required in digital and video signal processing.
AN APPROACH TO THE IDENTIFIABLE PARAMETERS OF A MANIPULATOR
(1994-10-01)
LIN, SK
;
交大名義發表
;
電控工程研究所
;
National Chiao Tung University
;
Institute of Electrical and Control Engineering
This article deals with the minimal parameters of a manipulator in the least squares sense, so that the minimal parameters are equivalent to the identifiable parameters. The least squares concept is used to introduce terminology for the minimal linear combinations (MLCs) of the system parameters that define a set of linear combinations of the system parameters. The number of elements of the set is minimal, vet the set still completely determines the system. Furthermore, it is shown that the problem of finding a set of MLCs of a manipulator can be simplified to that of finding two individual sets of MLCs that determine the entries of the inertia matrix and the gravity load. Although the approach is applied to the inertia constants of composite bodies to obtain a set of MLCs identical to an earlier one, the result is newly interpreted in the least squares sense. The approach itself is a new method for finding the identifiable parameters of a manipulator, and it yields some new insight into the manipulator dynamics. The crucial feature is that a set of MLCs found by using the present approach is guaranteed to be identifiable. The earlier approaches always require an identification method to verify the results. An equivalence theorem is also presented that rigorously states the equivalence between the different sets of minimal parameters. (C) 1994 John Wiley & Sons, Inc.
DIAGNOSIS OF SINGLE FAULTS IN BITONIC SORTERS
(1994-10-01)
LEE, TH
;
CHOU, JJ
;
電控工程研究所
;
電信工程研究所
;
Institute of Electrical and Control Engineering
Bitonic sorters have recently been proposed to construct along with banyan networks the switching fabric of future broadband networks [2]. Unfortunately, a single fault in a bitonic sorter may have disastrous consequences for the switching system. Therefore, a bitonic sorter must be proved to be free of faults before it can be used. In this paper we study the topological properties of bitonic sorters and present an efficient fault diagnosis procedure to detect, locate, and identify the fault type of single faults. Our diagnosis procedure can detect most single faults in two tests. Faults which cannot be detected in two tests can always be detected in four tests. Several binary search techniques are developed to locate a faulty sorting element (i.e,, a 2 x 2 sorter).
LOGIC SYNTHESIS FOR FIELD-PROGRAMMABLE GATE ARRAYS
(1994-10-01)
HWANG, TT
;
OWENS, RM
;
IRWIN, MJ
;
WANG, KH
;
資訊工程學系
In this paper, we consider the problem of configuring Field Programmable Gate Arrays (FPGA's) so that some given function is computed by the device. Obtaining the information necessary to configure a FPGA entails both logic synthesis and logic embedding. Due to the very constrained nature of the embedding process, this problem differs from traditional multilevel logic synthesis in that the structure (or lack thereof) of the synthesized logic is much more important. Furthermore, a metric-like literal count is much less important. We present a communication complexity-based decomposition technique that appears to be more suitable for FPGA synthesis than other multilevel logic synthesis methods. The key is that our logic optimization technique based on reducing communication complexity is good enough to allow a simple technology mapping to work well for FPGA devices.
THE EFFECT OF TRANSIENT GAIN COMPRESSION IN A SATURATED EDFA ON OPTICAL-TIME DOMAIN REFLECTOMETRY TESTING
(1994-10-01)
WAY, WI
;
LAI, YW
;
CHEN, YK
;
電信工程研究所
;
電信研究中心
This paper examines optical-time-domain-reflectometry (OTDR) pulse distortion due to transient gain compression in a saturated erbium-doped fiber amplifier (EDFA) and the resultant effect on testing long-haul optical fiber systems.
ELECTROLUMINESCENCE CHARACTERISTICS AND CURRENT-CONDUCTION MECHANISM OF A SI-C-H-P-I-N THIN-FILM LIGHT-EMITTING-DIODES WITH BARRIER LAYER INSERTED AT P-I INTERFACE
(1994-10-01)
JEN, TS
;
PAN, JW
;
SHIN, NF
;
HONG, JW
;
CHANG, CY
In order to improve the electroluminescence (EL) characteristics of the hydrogenated amorphous silicon carbide (a-SiC:H) p-i-n thin-film light-emitting diode (TFLED), a barrier layer (BL) was inserted at its p-i interface to enhance the hole injection efficiency under forward-bias operation. The a-SiC:H TFLED's with various optical gaps of BL had been fabricated and characterized. In addition, a composition-graded n+-layer was used to reduce its series and contact resistances to the Al electrode and hence the EL threshold voltage (V(th)) of an a-SiC:H BL TFLED. The highest obtainable brightness of an a-SiC:H BL TFLED was 342 cd/m2 at an injection current density of 600 mA/cm2 and the lowest EL V(th) achievable was 6.0 V. The current-conduction mechanism of an a-SiC:H BL TFLED had also been investigated. Within the lower applied-bias region, it showed an ohmic current, while within the higher applied-bias region, a space-charge-limited current (SCLC) was observed.
DESIGN-MODEL AND GUIDELINE FOR N-WELL GUARD RING IN EPITAXIAL CMOS
(1994-10-01)
HUANG, CY
;
CHEN, MJ
;
電子工程學系及電子研究所
;
電控工程研究所
;
Department of Electronics Engineering and Institute of Electronics
This work reports the development of design model for n-well guard rings in a CMOS process utilizing a low-doped epitaxial layer on a highly doped substrate. The validity of the model has been judged by a wide range of experimental data measured from the fabricated n-well guard ring structures with guard ring width as parameter. From the model developed, guideline has been drawn to minimize the guard ring width while critically suppressing the amount of electrons escaping from guard ring.
SURFACE-WAVE LEAKAGE PHENOMENA IN COUPLED SLOT LINES
(1994-10-01)
LIN, YD
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TSAI, YB
;
交大名義發表
;
傳播研究所
;
National Chiao Tung University
Surface wave leakage phenomena of coupled slot lines are investigated with spectral domain analysis. When the guided mode in the coupled slot lines changes from bound mode to leaky mode, there is a frequency range, called ''spectral gap,'' where only nonspectral solutions exist If the width of the center conductor or slots is increased beyond a certain value this spectral gap may disappear, resulting in a frequency range where both bound mode and leaky mode can exist simultaneously.