Browsing by Issue Date, starting with "2006-02-01"

Now showing 1 - 20 of 63776

雪泥
(2006-02-01)
管管
Optical properties of surface micromachining with randomly distributed etch holes
(2006-02-01)
Tien, CH
;
Lee, CH
;
光電工程學系
;
顯示科技研究所
;
Department of Photonics
Optical micromachining or microelectromechanical systems (MEMS) typically require etch holes to reduce the time required to release the micromechanical structure during the sacrificial undercutting. However, high-order diffraction beams generated by the periodic etch-hole array often deteriorate the optical performance by generating noise and erroneous crosstalk signals in. most optical systems. In this study, we examined the diffraction from a perforated micromirror and proposed a random distributed etch-hole layout. Due to the superposition of cosine functions with random periods, noise caused by high-order beams can be averaged effectively.
Memory effect on the inelastic interaction of electrons moving parallel to a solid surface
(2006-02-01)
Kwei, CM
;
Hsu, YH
;
Tu, YH
;
Tung, CJ
;
電子工程學系及電子研究所
It is generally assumed that two successive inelastic interactions between an electron and a solid are independent of each other. In other words, the electron has no memory of its previous interaction. However, the previous interaction of the electron generates a potential that should influence its succeeding inelastic interaction. The aim of this work is to establish a model to account for the memory effect of an electron between two successive inelastic interactions. On the basis of the dielectric response theory, formulae for differential inverse inelastic mean free paths (DIIMFPs) and inelastic mean free paths (IMFPs) considering the memory effect were derived for electrons moving parallel to a solid surface by solving the Poisson equation and applying suitable boundary conditions. These mean free paths were then calculated with the extended Drude dielectric function for a Cu surface. It was found that the DIIMFP and the IMFP with the memory effect for electron energy E lay between the corresponding values without the memory effect for electron energy E and previous energy Eo. The memory effect increased with increasing electron energy loss, E-0 - E-1 in the previous inelastic interaction. Copyright (c) 2005 John Wiley & Sons, Ltd.
雪泥
(2006-02-01)
管管
A compact DSP core with static floating-point arithmetic
(2006-02-01)
Lin, TJ
;
Lin, HY
;
Chao, CM
;
Liu, CW
;
Jen, CW
A multimedia system-on-a-chip (SoC) usually contains one or more programmable digital signal processors (DSP) to accelerate data-intensive computations. But most of these DSP cores are designed originally for standalone applications, and they must have some overlapped (and redundant) components with the host microprocessor. This paper presents a compact DSP for multi-core systems, which is fully programmable and has been optimized to execute a set of signal processing kernels very efficiently. The DSP core was designed concurrently with its automatic software generator based on high-level synthesis. Moreover, it performs lightweight arithmetic-the static floating-point (SFP), which approximates the quality of floating-point (FP) operations with the hardware similar to that of the integer arithmetic. In our simulations, the compact DSP and its auto-generated software can achieve 3X performance (estimated in cycles) of those DSP cores in the dual-core baseband processors with similar computing resources. Besides, the 16-bit SFP has above 40 dB signal to round-off noise ratio over the IEEE single-precision FP, and it even outperforms the hand-optimized programs based on the 32-bit integer arithmetic. The 24-bit SFP has above 64 dB quality, of which the maximum precision is identical to that of the single-precision FP. Finally, the DSP core has been implemented and fabricated in the UMC 0.18 mu m 1P6M CMOS technology. It can operate at 314.5 MHz while consuming 52mW average power. The core size is only 1.5 mmx1.5 mm including the 16 KB on-chip memory and the AMBA AHB interface.
High-reflectance composite metal coatings for planar-integrated free-space optics
(2006-02-01)
Gruber, M
;
Seiler, T
;
Wei, AC
;
光電工程學系
;
Department of Photonics
For planar-integrated free-space optical (PIFSO) systems high-reflectance thin-film coatings are crucial. Evaporated metal films are preferred for their relative technological simplicity. We propose a three-layer Al-Ag-Al coating composition that combines the high reflectance of Ag with the chemical passivity of Al and its good adherence to glass. Two special measures are taken to prevent delamination: one is an anchoring of the edges of the coating in narrow ditches that are etched into the substrate and the other is the use of an adhesive Al underlayer; to reduce absorption this underlayer is implemented only in sparsely distributed discrete areas. The optical properties of such composite coatings are investigated theoretically. The fabrication complexity is only slightly increased compared to PIFSO systems with one-layer Al reflectors. In experimental tests we verified a reflectance of approximately 98% and an adherence comparable to that of simple Al coatings. (c) 2006 Optical Society of America.
Voice over wireless local area network
(2006-02-01)
Shen, XM
;
Lin, YB
;
Pang, AC
;
Pan, JP
;
資訊工程學系
An optimal yield mapping approach for the small and medium sized liquid crystal displays
(2006-02-01)
Wang, PS
;
Su, CT
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
The ability to improve yield in the manufacturing process is an important competitiveness determinant for LCD factories. The TFT-LCD contains three major manufacturing sectors: the array, cell, and module assembly processes. The yield loss from the cell process is one of the most critical steps. To increase the cell process yield, more conforming LCD panels must be produced from one glass substrate. The sorter is a robot used in LCD manufacturing systems to achieve higher yield for matching TFT and CF plates. This sorter contains several ports that can transfer CF glasses from CF cassettes to match TFT glasses. In this paper, the Hungarian method is applied to solve the yield-mapping problem with the sorter. This method provides an optimal solution to improve the cell process yield.
Study of parallel coupled-line microstrip filter in broadband
(2006-02-01)
Chen, CC
;
Kuo, JT
;
Jiang, MS
;
Chin, A
;
傳播研究所
A parallel coupled-line microstrip filter is designed and implemented on PCB with its maximum bandwidth. In this paper, this filter has presented almost very good characteristics including the simulated bandwidth of 67%. the measured bandwidth of 64%, lower insertion loss of 1.27 dB. and flat response in the pass-band. The maximum bandwidth fabricated on PCB shows good agreement with the theoretically calculated bandwidth of 70% due to the narrower gap size between the coupled lines. (C) 2005 Wiley Periodicals, Inc.
Optimisation of the GTA welding process using the Taguchi method and a neural network
(2006-02-01)
Lin, HL
;
Chou, CP
;
機械工程學系
;
Department of Mechanical Engineering
There are many parameters that affect gas tungsten arc (GTA) welding process quality. Conventionally, the Taguchi method has been widely used in engineering; however, with this method the desired results can only be obtained with the use of very discrete control factors, thus leading to uncertainty about the real optimum. In this study, the Taguchi method was used for the initial optimisation of the GTA welding process parameters. A neural network was then used to construct the relationships between the welding process parameters and weld pool geometry of each weldment. The optimal parameters of the GTA welding process were determined by simulating significant process parameters obtained by the Taguchi method. Experimental results are provided to illustrate the proposed approach.
A new lossy substrate de-embedding method for sub-100 nm RF CMOS noise extraction and modeling
(2006-02-01)
Guo, JC
;
Lin, YM
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new equivalent circuit method is proposed in this paper to de-embed the lossy substrate and lossy pads' parasitics; from the measured RF noise of multifinger MOSFETs with aggressive gate length scaling down to 80 run. A new RLC network model is subsequently developed to simulate the lossy substrate and lossy pad effect. Good agreement has been realized between the measurement and simulation in terms of S-parameters and four noise parameters, NFmin,, (minimum noise figure), R, (noise resistance), Re(Y-sopt), and Im(Y-sopt) for the sub-100-nm RF nMOS devices. The intrinsic NFmin extracted by the new de-embedding method reveal that NFmin at 10 GHz can be suppressed to below 0.8 dB for the 80-nm nMOS attributed to the advancement of f(T) to 100-GHz level and the effectively reduced gate resistance by multifinger structure.
Design of adaptive dynamic absorber to reduce optical disk drive vibration at multiple rotating speeds
(2006-02-01)
Chang, CS
;
Liu, TS
;
機械工程學系
;
Department of Mechanical Engineering
In this study, we design a dynamic absorber to reduce optical disk drive vibration at multiple rotating speeds using an enlarged bandwidth control at targeted rotating speeds. In addition to the basic absorber as a passive device, a voice coil motor serves to actively control vibration. Combining passive and active devices leads to far greater stability and robustness. The proposed dynamic absorber has been validated in simulations and experiments.
Development of an artificial neural network to predict lead frame dimensions in an etching process
(2006-02-01)
Liu, TC
;
Li, RK
;
Chen, MC
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
The electronic industry is rapidly developing, creating high demand for IC production. Etched semiconductor lead frames are the basic material used in IC packaging. IC packaging requires high-precision lead frames. The dimensions of the pilot hole are generally required to be highly precise in lead frame manufacturing. The photo-etching process must control the dimension of the pilot hole and record the manufacturing data of the etching machine and inspection data. This study presents the development of an artificial neural network (ANN) model that can be applied to construct the predicting model. The predictive model can estimate the dimensions of the pilot hole and thus determine the process parameters needed to improve lead frame quality in the etching process.
A full code-patterns coverage high-speed embedded ROM using dynamic virtual guardian technique
(2006-02-01)
Chang, MF
;
Chiou, LY
;
Wen, KA
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Crosstalk between bitlines induces read failure and limits the coverage of applicable code-patterns for high-speed contact/via-programming read-only memories (ROMs) in SoC. Owing to the variation in bitline loading across code-patterns, the amount of coupled noise on an accessed bitline is code-pattern-dependent. This crosstalk effect worsens, with larger coupling capacitance and smaller intrinsic loading, as the technology node shrinks. This study proposes dynamic virtual guardian (DVG) techniques for contact/via-programming ROM macros and compilers to eliminate the crosstalk-induced read failure and increase the code-patterns coverage. Compared with conventional ROMs, DVG techniques achieve higher speed, lower power consumption and better design for manufacturing (DFM) capability with full code-patterns coverage. Experiments on fabricated designs, a conventional ROM and two 256 Kb DVG ROMs, using 0.18 mu m 1P5M CMOS technology have demonstrated that DVG techniques achieve 100% code-pattern coverage under a small sensing margin.
A novel master switching method for electronic cam control with special reference to multi-axis coordinated trajectory following
(2006-02-01)
Chang, YH
;
Chieng, WH
;
Liao, CS
;
Jeng, SL
;
機械工程學系
Multi-axis coordinated trajectory following is important in CNC machines and metal cutting tools. Recently, flight simulators with electrical actuators have been in increasing demand. However, the coordinate control scheme affects the accuracy of the motion because motors have an insufficient load-capacity relative to the hydraulic actuators. The electronic cam (ECAM) is typically used to perform coordinated control. However, selection of the master may determine potentially very different characteristics of motion. This study proposes an automatic master switching method. The conditions and results of the master switching method for ECAM are detailed. The robustness and stability of the proposed control system is also demonstrated using the well-known structured perturbation analysis tool, mu. (c) 2005 Elsevier Ltd. All rights reserved.
Quinoxalines incorporating triarylamines: Dipolar electroluminescent materials with tunable emission characteristics
(2006-02-01)
Huang, TH
;
Whang, WT
;
Zheng, HG
;
Lin, JTS
;
材料科學與工程學系
Dipolar compounds (abbreviated as QuPy) featuring quinoxaline acceptors and diarylamine or triarylamine donors were prepared via palladium-catalyzed C-N or C-C bond formation in good yields. They possess high thermal stability with a high decomposition temperature (T-d > 400 degrees C) and exhibit no crystalline character. The emission colors of the materials vary from green to orange red and are dependent on the nature of the electron-withdrawing segments and solvents. Two types of double-layer organic light-emitting diodes (OLEDs) were constructed using these dipolar compounds as hole-transporting/emitting layers and TPBI or Alq(3) as an electron-transporting layer: (I) ITO/QuPy/Alq(3)/Mg:Ag and (II) ITO/QuPy/TPBI/Mg:Ag (TPBI = 1,3,5-tris(N-phenylbenzimidazol-2-yl)-benzen; Alq(3) = 1,3,5-tris(N-phenyl-benzimidazol-2-yl)-benzene). The recombination zone in most of those devices were confined in the quinoxaline layers, The green to orange colors in these devices correspond well with the film PL of the material used. The relation between the energy levels of the compounds and the performance of the light-emitting diode are discussed.
Cyclic tests of post-tensioned precast CFT segmental bridge columns with unbonded strands
(2006-02-01)
Chou, CC
;
Chen, YC
;
土木工程學系
;
Department of Civil Engineering
Two ungrouted post-tensioned, precast concrete-filled tube (CFT) segmental bridge columns were tested tinder lateral cyclic loading to evaluate the seismic performance of the column details. The specimens included a load stub, four equal-height circular CFT segments, and a footing. Strands were placed through the column and post-tensioned to provide a precompression of the column against the footing. One specimen also contained energy-dissipating devices at the base to increase the hysteretic energy. The test results showed that (1) both specimens could develop the maximum flexural strength at the design drift and achieve 6% drift with small strength degradation and residual displacement, (2) the proposed energy-dissipating device could increase energy dissipation in the hysteresis loops, and (3) the CFT segmental columns rotated not only about the base but also about the interface above the bottom segment. This study proposed and verified a method to estimate the experimental flexural displacement using two plastic hinges in the segmental column. Copyright (c) 2005 John Wiley & Sons, Ltd.
New pixel circuits for driving active matrix organic light emitting diodes
(2006-02-01)
Chen, BT
;
Tai, YH
;
Kuo, YJ
;
Tsai, CC
;
Cheng, HC
New pixel circuit designs for active matrix organic light emitting diodes (AMOLEDs), based on the low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) were proposed and verified by SPICE simulation and fabrication results. Threshold voltage compensation pixel circuits consisting of five TFTs, one additional control signal, and one storage capacitor were used to enhance display image uniformity. The simulation and measured results show that this pixel circuit has high immunity to the variation of poly-Si TFT characteristics. (c) 2006 Elsevier Ltd. All rights reserved.
Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: Design concept and circuit implementations
(2006-02-01)
Ker, MD
;
Lin, KH
;
電機學院
;
College of Electrical and Computer Engineering
Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nano-scale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification and analysis of ESD protection designs for mixed-voltage I/O interfaces, and the designs of high-voltage-tolerant power-rail ESD clamp circuit are presented and discussed.
Yield improvement planning for the recycle processes of test wafers
(2006-02-01)
Wu, MC
;
Chien, CS
;
Lu, KS
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
Test wafers are used to measure the process quality in semiconductor manufacturing. Test wafers are reusable by recycle cleaning and can be downgraded to the downstream processes. Most previous studies on test wafers aimed to reduce the use of test wafers by making appropriate operational decisions. Yet, the effective improvement of yield in the recycle process of test wafers is seldom explored. This paper formulates a decision problem and proposes two solution methods for selecting the yield improvement alternatives in the test wafer recycle processes. The decision problem is to determine the yield improvement target for each recycle process in order to minimize the use of test wafers, under a given budget for yield improvement. The two solution methods involve a genetic algorithm and a marginal allocation algorithm. The two methods yield very close solutions, but the marginal allocation method is better because it requires less computation time.