標題: ESD protection circuit
作者: Ker
Ming-Dou
Lin
Kun-Hsien
公開日期: 29-八月-2006
摘要: The claimed invention discloses an ESD protection circuit that is applied to an IC with power-down-mode operation. When the IC goes into power-down-mode operation, leakage current and charging from the I/O pad to the VDD power line could be prevented by applying the present invention. Therefore, the malfunction of the IC can be avoided. There still have two ESD clamp circuits respectively connected between the VDD power line and the VSS power line and between ESD bus line and VSS power line, so as to achieve the whole chip ESD protection scheme. The present invention can prevent ESD protection circuit from resulting in leakage current or malfunction under power-down-mode operation, and moreover achieve whole chip ESD protection scheme.
官方說明文件#: H01L023/62
URI: http://hdl.handle.net/11536/104804
專利國: USA
專利號碼: 07098511
顯示於類別:專利資料


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