Microarchitecture-aware floorplanning for processor performance optimization

Abstract

Previous generation floorplanners had objectives focused on smaller area and wirelength. These objectives were considered sufficient since the latencies of interconnects could be neglected. As technology advances and feature size continues to shrink, the communication of signals on interconnects becomes multi-cycled, hence the latencies can not be ignored. These interconnect latencies have impacts on the performance of the processor, and most of state-of-the-art floorplanning frameworks do not consider these issues. In this paper, we propose a methodology based on a heuristic for better performance in terms of microarchitecture and floorplanning, and it is more efficient than previous works shown in the literature. The experimental results from a subset of MIPS show that our methodology can better the processor performance. The perfomance has been improved by up to 35.75% when compared to the floorplanning results from conventional objectives, with few extra overhead on area and wirelength. We also found that the intuition of pressing wirelength for floorplan optimization may not get performance edge.