標題: | A low-power Viterbi decoder based on scarce state transition and variable truncation length |
作者: | Lin, Dah-Jia Lin, Chien-Ching Chen, Chih-Lung Chang, Hsie-Chia Lee, Chen-Yi 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2007 |
摘要: | The ACS computation and the survivor memory are most power critical, consuming about 90% power in the Viterbi decoder. Based on the low power mechanisms, the scarce state transition (SST) technique and the variable truncation length, we present a Viterbi decoder for the MB-OFDM UWB applications. The SST scheme lowers state transition as well as signal switches in the ACS units. Moreover, the decoding with variable truncation length leads to the access reduction in the survivor memory. The experimental results show more than 30% power reduction under high SNRs as compared to those without SST and variable truncation length. |
URI: | http://hdl.handle.net/11536/12312 |
ISBN: | 978-1-4244-0582-4 |
期刊: | 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Proceedings of Technical Papers |
起始頁: | 99 |
結束頁: | 102 |
顯示於類別: | 會議論文 |