| 標題: | 積體電路與電子系統之靜電放電防護技術產學聯盟( II ) Consortium of ESD Protection Technology for Circuits and Systems( II ) |
| 作者: | 國立交通大學電子工程學系及電子研究所 |
| 公開日期: | 2015 |
| 官方說明文件#: | MOST104-2622-E009-003 |
| URI: | http://hdl.handle.net/11536/130153 https://www.grb.gov.tw/search/planDetail?id=11359693&docId=458703 |
| 顯示於類別： | 研究計畫 |
- 積體電路與電子系統之靜電放電防護技術產學聯盟( III ) / 柯明道
- 積體電路與電子系統之靜電放電防護技術產學聯盟( I ) / 柯明道;KER MING-DOU
- Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs / Chen, Shih-Hung;Ker, Ming-Dou
- Design on ESD protection scheme for IC with power-down-mode operation / Ker, MD;Lin, KH
- Substrate-triggered ESD protection circuit without extra process modification / Ker, MD;Chen, TY
- Overview on ESD Protection Designs of Low-Parasitic Capacitance for RF ICs in CMOS Technologies / Ker, Ming-Dou;Lin, Chun-Yu;Hsiao, Yuan-Wen
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