具非揮發性記憶體之多核心處理器電源與記憶體管理

Abstract

隨著記憶體需求擴大及對其存取速度要求，記憶體消耗功率與面積也不斷攀升，因此有越來越多研究開始考慮使用非揮發性記憶體(Nonvolatile Memory)取代部份傳統記憶體以降低系統的靜態功率消耗。然而這方面的研究較少以軟硬體整合後的系統運作為出發點，考慮未來作業系統在搭配具非揮發性記憶體的多核心處理器下的記憶體配置和管理機制，此外考慮在記憶體各階層中存在非揮發性記憶體後，將產生更多且不同特性的多核心處理器耗電模式(Power mode)，電源管理策略(Power management)也必須重新檢討。本計畫的主要目的在研究具備非揮發性記憶體之多核心處理器的作業系統技術，尤其著重於耗電與記憶體管理，並嘗試以系統模擬與分析的方式研究此類多核心處理器晶片的計算機與記憶體架構。 本計畫希望以三年時間，進行下面問題的探討，首先不同類型的應用程式情境(Application Scenarios)往往具備截然不同的資料與指令記憶體(Data and Instruction Memory)存取行為和所需記憶體的容量，因此我們將從不同類型、特性之應用程式情境出發，以效能、耗能與面積為三主要考量點，利用系統模擬分析的方式探討最佳非揮發性記憶體階層架構。因應非揮發性記憶體系統在各記憶體階層的架構與設計，未來多核心處理器所提供的耗電模式以及電源管理功能勢必有很大的擴充與改變，因此我們將研究具非揮發性記憶體之多核心系統中的電源管理策略與機制。最後我們將分析各應用程式之程式階段(Program Phase)對指令(Instruction)與資料(Data)記憶體的存取的需求和特性，借此資訊改進作業系統中對各類型記憶體空間的動態分配與管理機制。

Recently, the power consumption and size of memory for computer systems increase dramatically due to high demanding on memory spaces and memory access speeds. Therefore, to use non-volatile memory in the memory hierarchy which can significantly reduce static power consumption of memory attracts considerable interests from both industries and academia. However, very few studies investigate issues when we integrate application and system software and multi-core processors with non-volatile memory. In this project, we study the operating system design for multi-core processors with non-volatile memory. More specifically, we investigate the memory management and power management in OS for supporting multi-core processors with non-volatile memory. Moreover, we would like to examine the processor architecture and memory hierarchy for supporting different application scenarios based on a system level simulation. In this project, we plan to use three years to research the following issues. First, different types of applications such as mobile devices, multimedia devices, servers, etc. tend to have very different size demands and access behaviors of data and instruction memory. We would like to evaluate the performance, power consumption, and size of chipsets for multi-core processors with non-volatile memory in the memory hierarchy under different application scenarios. A full system and instruction level simulator with reconfigurable processor and memory architectures will be developed and used for the evaluation. Second, with non-volatile memory in the memory hierarchy, we expect multi-core processors can provide more power modes and power management features. The power management software in the OS needs future studies and re-designs. Finally, we will analyze the instruction and data memory demands and access characteristics for each program phase of an application. Based on the information, we would like to improve the memory management mechanisms in the OS for dynamical memory allocation and management.