標題: | A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis |
作者: | Lin, Chen-Yang Wong, Cheng-Chi Chang, Hsie-Chia 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2012 |
摘要: | This paper presents a turbo decoder chip which can decode code rate k/(k + 1) constituent convolutional codes for k = 1, 2, 4, 8, and 16. After replacing the constituent code by its code rate 1/(k + 1) reciprocal dual code, we can derive a smaller codeword space and design a simpler decoding trellis structure for high code-rate SISO decoder. In addition, two parallel SISO decoders are exploited in our turbo decoder by using the quadratic permutation polynomial (QPP) interleaver to improve the decoding speed. After fabricated in 1P9M CMOS 40 nm process, the proposed decoder with 1.27 mm(2) core area can achieve 535 Mbps throughput at 8/9 code rate, and the energy efficiency is 0.068 nJ/bit/iteration at 0.9 V. |
URI: | http://hdl.handle.net/11536/134767 |
ISBN: | 978-1-4673-2771-8 |
期刊: | 2012 IEEE Asian Solid State Circuits Conference (A-SSCC) |
起始頁: | 197 |
結束頁: | 200 |
顯示於類別: | 會議論文 |