標題: Adaptive quadrature clock generator
作者: Huang, Juin-Hau
Lin, Chih Hsien
Jou, Shyh-Jye
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2006
摘要: In this paper we propose the architecture for multi-phases clocking distribution. Based on QCG architecture, we propose a new adaptive QCG to increase its operation frequency range. The adaptive QCG can automatically track and lock phase difference when input frequency is different. This architecture is implemented by UMC 0.13 mu m IP8M process and employed by on-chip transceiver. The average power consumption is 6.43 mW at 2 GHz clocking frequency. The operation frequency is from 500 MHz to 2.5 GHz.
URI: http://hdl.handle.net/11536/135217
ISBN: 1-4244-0179-8
期刊: 2006 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PAPERS
起始頁: 203
結束頁: +
顯示於類別:會議論文