使用平行處理時間數位轉換器與相位內插數位控制振盪器之快速鎖定全數位鎖相迴路

Abstract

鎖相迴路用於產生穩定且具參考價值的時脈訊號，以便系統操作規律有秩序，作為電路心臟持續提供穩定之時脈訊號，近年來廣泛使用在SOC (System On Chip)應用上，更是攜帶式、通訊用等電子產品中不可或缺的角色。類比鎖相迴路已經有數十年的發展歷史，但是近年來為了能配合製程微縮以及降低晶片成本等考量下，數位式鎖相迴路電路之優點和需求逐漸被彰顯出來，展露出取代類比式之姿。 在本篇論文中，以全客戶式設計完成全數位鎖相迴路，第一顆晶片設計概念為跳脫傳統時間數位轉換器以串級方式依解析度大小處理的迷思，將不同解析度的時間數位轉換器採平行架構方式處理相位誤差，如此可縮短整體運算時間，並能達到節省功耗的效果。除此之外將數位控制振盪器加入相位內差的機制，可減少頻率的跳動以達到較精準的鎖定頻率，降低輸出訊號的抖動，設計採用週期線性的數位控制振盪器，振盪頻率範圍為273MHz~1110MHz。 第二顆晶片以第一顆晶片電路為基礎，加入外部可調式除頻器，使輸出訊號可鎖定至不同頻率，讓此鎖相迴路系統變得更為實用。再配合快速鎖定機制，電路一開始運作即可運算並跳至目標頻率附近，避免鎖定至不同頻率的時間差異過大，有效提升整體鎖相迴路的效能。 第一顆晶片輸出頻率鎖定至800MHz，量測結果包含1.51ps的方均根時間抖動(RMS Jitter)與7.56ps的峰對峰值時間抖動(Peak-to-Peak Jitter)，平均功率消耗為11.34mW，晶片核心面積為0.1mm2。而第二顆晶片模擬800MHz的平均峰對峰值時間抖動(Peak-to-Peak Jitter)為4.71ps，平均功率消耗為11.7mW，晶片核心面積為0.128mm2。

Phase-locked loops (PLL) generate a stable clock signal as a reference siganl to ensure circuits operate correctly. Nowadays, PLLs are widely used for SOC applications, such as wireless communication synthesizers, so it is indispensable in many applications. The analog phase-locked loop (APLL) has been developing for several years. However, in recent years, the all-digital phase-locked loop (ADPLL) has been gradually more mature, and it reveals its potential to replace the APLL. In this thesis, we implement the ADPLL by using full-custom design flow. The design concept of the first chip is, instead of the traditional time-to-digital converter (TDC) using cascade architecture, using a parallel processing TDC to reduce the operation time and the dynamic power consumption. In addition, the digitally controlled oscillator (DCO), adopting the interpolated mechanism, can reduce the output frequency Jitter in order to achieve a more accurate locking frequency. The proposed DCO with a linearly periodic structure has the operation range from 273MHz to 1110MHz. The design of the second chip, based on the first chip, adds an external adjustable divider so that the output signal can be locked to different frequencies. With the additional frequency tracking engine (FTE), the output can jump to the target frequency quickly to reduce the locking time. Therefore, the overall performance of the PLL is further improved. The output frequency of the first chip is locked at 800MHz. The measurement results show the RMS Jitter of 1.51ps, the Peak-to-Peak Jitter of 7.56ps, average power consumption of 11.34mW, and the core area of 0.1mm2. While the second chip locks at 800 MHz, simulation results show the Peak-to-Peak Jitter of 4.71ps, average power consumption of 11.7 mW, and the core area of 0.128 mm2.