標題: A Fast-Locking All-Digital Phased-Locked Loop with a 1 ps Resolution Time-to-Digital Converter Using Calibrated Time Amplifier and Interpolation Digitally-Controlled-Oscillator
作者: Chu, Hsing-Chien
Hua, Yi-Hsiang
Hung, Chung-Chih
電機工程學系
Department of Electrical and Computer Engineering
關鍵字: All-digital phase-locked loop (ADPLL);time-to-digital converter (TDC);time amplifier (TA);digitally-controlled-oscillator (DCO)
公開日期: 2016
摘要: This paper presents an all-digital phase-locked loop (ADPLL) in the 0.18 mu m CMOS process, which uses a multi-stage time-to-digital converter (TDC) with calibration and interpolation digitally-controlled-oscillator (IDCO). The ADPLL also utilizes a frequency tracking engine (FTE) to reduce the system locking time. The ADPLL has a frequency range of 149-1450 MHz, the minimum peak-to-peak jitter achieves 21.9 ps, and the TDC shows the minimum resolution of 1 ps. The power dissipation of the ADPLL is 18.2 mW at 800 MHz.
URI: http://hdl.handle.net/11536/134658
ISBN: 978-1-5090-1830-7
期刊: 2016 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC)
起始頁: 375
結束頁: 378
顯示於類別:會議論文