A Fast-Locking All-Digital Phased-Locked Loop with a 1 ps Resolution Time-to-Digital Converter Using Calibrated Time Amplifier and Interpolation Digitally-Controlled-Oscillator

Abstract

This paper presents an all-digital phase-locked loop (ADPLL) in the 0.18 mu m CMOS process, which uses a multi-stage time-to-digital converter (TDC) with calibration and interpolation digitally-controlled-oscillator (IDCO). The ADPLL also utilizes a frequency tracking engine (FTE) to reduce the system locking time. The ADPLL has a frequency range of 149-1450 MHz, the minimum peak-to-peak jitter achieves 21.9 ps, and the TDC shows the minimum resolution of 1 ps. The power dissipation of the ADPLL is 18.2 mW at 800 MHz.