標題: A fast-lock-in ADPLL with high-resolution and low-power DCO for SoC applications
作者: Sheng, Duo
Chung, Ching-Che
Lee, Chen-Yi
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2006
摘要: In this paper, we propose a fast-lock-in all-digital phase-locked loop (ADPLL), which is designed with the cell library and described by Hardware Description Language (HDL). The proposed ADPLL uses a novel 2-level flash time-to-digital converter (TDC) to lock in within 2 reference clock cycles. The novel digitally controlled oscillator (DCO) achieves high-resolution with 0.93ps resolution and can extend the controllable range easily. In addition to high-resolution, the power consumption of the proposed DCO can be lowered as 110 mu W(@200MHz). The proposed ADPLL can be easily ported to different process as a soft intellectual property (IP), making it very suitable for System-On-Chip (SoC) applications as well as system-level power management
URI: http://hdl.handle.net/11536/17449
ISBN: 978-1-4244-0386-8
期刊: 2006 IEEE Asia Pacific Conference on Circuits and Systems
起始頁: 105
結束頁: 108
顯示於類別:會議論文