適用於高速時脈產生之低功率全數位式頻率合成器

Abstract

本論文提出一個新的數位控制頻率振盪器及一個新的相位頻率偵測器之架構以設計一個低功率的全數位式鎖相迴路。藉由使用一新型的數位控制延遲元件，此顆數位控制頻率振盪器可具有其絕對單調的特性，且使的數位控制頻率振盪器的設計更為容易。此外，我們也提出了一個新的相位頻率偵測器，它可以在一個參考時脈週期內，完成頻率和相位的比較，並且能進一步調整振盪器的振盪頻率。 此全數位式頻率合成器是以TSMC 0.13um技術來做設計。它的輸出頻率範圍可從三百百萬赫茲到一千百萬赫茲，並且可以在十六個參考時脈週期內達到鎖定(最差的情況下)。輸出時脈訊號的鋒對鋒抖動值亦可維持在120ps之內。在供應電壓為1.2伏，操作頻率在1千百萬赫茲的情況下，此全數位式頻率合成器所消耗的總功率為3.1毫瓦。此外，參考現有的高速時脈應用之規格，此頻率合成器可作為高速數位訊號處理器的時脈產生器。

This thesis proposes a new digital controlled oscillator (DCO) and a new phase frequency detector (PFD) architecture for the all digital phase-locked loop (ADPLL) with low power design. By using the new type digitally controlled delay element (DCDE), a digitally controlled oscillator (DCO) with characteristics of its monotonicity is presented, which makes the DCO design more straightforward. Besides, a new PFD architecture that can finish phase and frequency comparison and adjustment in one reference cycle is also presented. The proposed ADPLL-based frequency synthesizer has been designed with TSMC 0.13um technology model. It can operate from 300 MHz to 1 GHz, and achieve frequency acquisition within sixteen reference clock cycles (worst case scenario). The peak-to-peak jitter of the output clock is less than 120 ps. Total power dissipation of the ADPLL-based frequency synthesizer is 3.1 mW at 1 GHz with a 1.2 V power supply. With the specification, it could be used for high speed clock generation in high speed DSPs applications.