全數位鎖相迴路之相位追蹤與頻率追蹤控制器設計

Abstract

現代的系統單晶片(SoC) 需要晶片內部的時脈產生器用以產生不同的頻率來給予內部其他的子系統使用，一般而言以鎖相迴路為基礎的時脈產生器來達到此目的。為了減少抖動量及增加迴路的穩定度，必須依照輸出頻率及倍數來調整設計參數，然而現今的類比鎖相迴路需要較長的設計週期。 相較而言以全數位的方式實作鎖相迴路更能節省系統晶片整合的成本。然而現今大部分的數位鎖相迴路仍是以追蹤頻率為主要考量，如此之下在部分與相位誤差有關的應用中，全數位鎖相迴路便不適用於此應用當中。在本文中將提出以相位為主的追蹤演算法，使全數位鎖相迴路更能適應於各類應用當中。此外在僅使用單一數位控制震盪器的前提下，提出一個低輸出擾動，高效率的追蹤演算法。為了達到此目的，一個便於分析相位頻率分析的相位狀態圖將被提出。為了解決雙數位控制震盪器所導致的不匹配問題，根據此相位狀態圖，一個類數位訊號處理器的架構將被提出。綜合以上所有，一個全新可移植整合的全新架構的全數位鎖相迴路將被提出在此篇論文當中。

Modern system-on-a-chip (SoC) processors often require on-chip clock generation and multiplication to produce several unrelated frequencies for other sub-systems. The PLL is common way of frequency multiplication to accomplish the task. In order to minimize the jitter and insure the stability for each output frequency, the design parameters need to change according to the output frequency and multiplication factors. Conventional analog skills suffer from long design cycle. In SoC design, it can save more time when we use the all-digital skill to implement the PLL. However, most of current ADPLL controlled only discuss with the frequency tracking. Under this situation, the ADPLL cannot meet the requirements of some applications, which is depended on the phase error. This thesis provides a phase tracking based algorithm, thus the proposed ADPLL can be portable in varied applications. Furthermore, the proposed tracking algorithm has high efficiency and low output jitter. The proposed ADPLL with single DCO solves the mismatch problem in clock pair architecture. Moreover, DSP based architecture is proposed to provide a programmable and stable ADPLL. In order to realize All-Digital PLL, new approaches be presented to offer portable, full-integration and low-jitter frequency synthesizer in digital VLSI.