全數位式鎖相迴路的分析與設計

Abstract

我們在本篇論文提出一個全數位式鎖相迴路的設計，它由數位控制振盪器、相位頻率偵測器、控制單元和一些輔助的邏輯電路所組成。藉由詳細地分析與設計每一個功能方塊，我們指出重要的設計參數並討論一些設計上的問題。在我們的設計中，數位控制振盪器由四條路徑、二個模式和一個5位元可控制延遲細胞元所構成，這個可控制延遲細胞元是數位式控制的電流調節型反向器。我們採用一顆D型正反器當作相位頻率偵測器。控制單元執行二個主要的功能：頻率搜尋演算法和相位追蹤演算法，頻率搜尋演算法很像二位元樹搜尋法，此外，被我們提出來的相位追蹤演算法是以減少累積的相位誤差而不降低追蹤的速度為目的。我們以全客戶式的設計方式實現數位控制振盪電路，並以細胞元的設計方式實現其餘的電路。為了快速地評估電路架構和演算法，我們把數位控制振盪電路以Verilog的模形來模擬，並以Verilog模擬器來驗証整個全數位式鎖相迴路的系統。我們以0.35微米互補式金屬氧化半導體製程來實現整個系統，此系統大約需要50個參考時脈週期將累積的相位誤差縮小到10%之內，數位控制振盪電路可產生360到625百萬赫茲的時脈，它是參考時脈頻率的兩倍。

In this thesis, we have presented the design of an all-digital phase-locked loop (ADPLL), which consists of a digitally controlled oscillator (DCO), a phase frequency detector (PFD), a control unit and some auxiliary logic circuits. By analyzing and designing each functional block in detail, we point out the important design parameters and discuss some design issues. The DCO consists of four paths, two modes, and a 5-bit controlled delay cell. The delay cell is a digitally controlled current-starved inverter. We adopt a D flip-flop as our PFD. The control unit performs two major functions, i.e., frequency search algorithm and phase tracking algorithm. Frequency search algorithm is similar to binary tree search. In addition, a phase tracking algorithm is proposed to reduce the accumulative phase error without slowing down the tracking speed. We implement the DCO by full custom design style while the other circuits are implemented by cell-based design style. In order to rapidly evaluate the structures and algorithms, we model the DCO in Verilog construct, and verify the ADPLL system by Verilog simulator. The ADPLL is designed in 0.35 um COMS SPQM technology. It needs about 50 reference cycles to make the accumulative phase error smaller than 10%. The DCO can generate frequency from 360 to 625 MHz, which is two times reference clock frequency.