應用於0.5V全數位鎖相迴路的電壓源靈敏度補償機制

Abstract

本篇論文提出一個應於0.5V全數位鎖相迴路的電壓源靈敏度補償機制，此設計包含三大部分：全數位鎖相迴路、4-bit可調式補償電路以及數位偵測電路。本補償機制設計為Foreground執行，意即在每次電源開啟時執行偵測以尋找最佳化補償值，而本機制利用全數位鎖相迴路中部份元件即可達成簡單粗略的抖動偵測並依此結果來完成搜尋，當搜尋完成數位偵測電路將關閉避免多餘功耗產生。全數位鎖相迴路操作電壓為0.5伏特，輸出頻率為400MHz，時脈抖動為74ps，功率消耗為120.3uW。當電壓源雜訊為峰對峰值10mV頻率10kH的正弦波時，時脈抖動為370ps，經過補償後時脈抖動為101.9ps。此晶片使用TSMC 90nm 1P9M製程實現，晶片佈局面積為0.438 mm^2。

This thesis proposes a supply sensitivity compensation scheme for a 0.5V all-digital phase-locked loop. This design includes an ADPLL, a 4-bit adjustable compensation circuit, and a digital detect circuit. The compensation scheme is designed for foreground execution, which means it detects and finds the best compensation value every time when the power is on. The scheme uses some components of the ADPLL to do jitter measure and follow the result to search the compensation value. After the search is complete, the detection circuit is shut sown to avoid unnecessary power consumption. The power consumption of the ADPLL is 120.3uW for a supply voltage of 0.5V and an operating frequency of 400MHz. It’s peak-to-peak jitter is 74ps. For a noise of 10mV 10kHz sinusoidal waveform on the supply voltage, the peak to peak jitter without and with compensation are 370ps and 101.9ps. This chip will be fabricated in TSMC 90nm 1P9M process, with an area of 0.438 mm^2.