全數位鎖相迴路之研究與設計

Abstract

我們在本篇論文中將提出一個全數位鎖相迴路的設計，它是由相位偵測器，頻率偵測器，數位控制震盪器，控制單元與一些邏輯電路所組成。我們將提出一個新的相位追蹤演算法，此演算法擁有減少相位累增誤差的功能，且不會降低追蹤的速度，及一個能消除元件內部延遲誤差的改良頻率偵測器，並將詳細的介紹每一工作單元的動作原理與在設計時所要注意的問題。在我們所設計的全數位鎖相迴路中，數位震盪器它是由三條路徑與三個模式及5-bit的delay cell所組成。我們控制單元主要執行兩個動作：一是頻率搜尋演算法，另一個是相位追蹤演算法，在頻率搜尋時，我們採用兩個D型正反器與一些邏輯電路組成頻率偵測器，用來偵測頻率的差異，而在相位追蹤時，我們採用兩個並聯的D型正反器來當做我們的相位偵測器。最後我們將以Hspice與Verilog的模型來模擬，並以Verilog的模擬環境來驗證我們整個全數位鎖相迴路的系統。

In this thesis, we present the design of an all digital phase locked loop (ADPLL), which consists of a phase detector (PD), a frequency detector (FD), a digitally controlled oscillator (DCO), a control unit and some auxiliary logic circuits. A new phase tracking algorithm is proposed to reduce the accumulative phase error without slowing down the tracking speed, and a modify frequency detector circuit which can cancel the internal error delay. We analyze and design each functional block in detail, and point out the important design parameters and discuss some design issues. In our design, the DCO consists of three paths, three modes, and a 5 bit controlled delay cell. The control unit performs two major functions, i.e., frequency search algorithm and phase tracking algorithm. We use two D-type flip-flops and some logic circuits for frequency detector to detect the difference of frequency in searching frequency. At the same time, we use two parallel D-type flip-flops for phase detector to track phase. Finally, we use Hspice and Verilog code to verify the overall ADPLL system