超低功率高面積使用率全數位鎖相迴路頻率合成器

Abstract

本論文提出一個運用所提出的低功率演算法的全新全數位鎖相迴路架構。低功率的搜尋演算法能使我們的全數位鎖相迴路在22個參考週期內完成相位鎖定，而且可以使硬體方面簡單及面積小的優點。並且在論文中提出的低功率數位控制震盪器具有兩種架構，第一種適合用在高速下，而第二種適合用在寬的頻率範圍。這兩種數位控制震盪器都可以使全數位鎖相迴路更加地省電。提出的邏輯及閘鎖存器為基礎的頻率相位偵測器可以偵測多種參考頻率的倍數。總體而言，我們所提出的全數位鎖相迴路具有面積小以及低功率消耗的特性。

本論文以TSMC 0.13um 1P8M CMOS 技術實現。供給電壓為1.2伏，總面積為0.0041mm2。模擬結果顯示當數位控制震盪器頻率為700萬赫茲時，全數位鎖相迴路的相位抖動為18.4ps,1.38%(Pk-Pk)，而總功率消耗為0.85mW。

A new all digital phase-locked loop (ADPLL) architecture with low power algorithm is presented in this thesis. The proposed low power search algorithm can accomplish phase lock process within 22 input clock cycles and make the hardware simple, area small. In thesis, proposed low power digitally controlled oscillator (DCO) has two types. The two types of proposed DCO make proposed ADPLL lower power. The proposed NAND latch based Phase-Frequency-Detector (PFD) can detect multi times of reference frequency .This ADPLL has characteristics of small area cost and lower power consumption.

The proposed ADPLL is simulated and implemented by TSMC 0.13um 1P8M CMOS technology. The supply voltage is 1.2v and total area is 0.0041mm2. The simulation results show that when the DCO operates at 700MHz, the jitter is 18.4ps, 1.38% (Pk-Pk) and the total power consumption of ADPLL is 0.85mW.