應用於序列傳輸系統之突發式時脈資料回復電路與全數位式展頻時脈產生器

Abstract

隨著現代製程科技進展往小尺寸以及低功耗的發展，更能滿足不同的系統單晶片內部大量的運算以及彼此間的高速資料傳輸。高速傳輸介面規格則朝向每秒幾十億位元的低抖動及符合能源效益(~1皮焦耳每位元)的傳輸速度來進化。在資料傳輸器端則利用展頻時脈產生器來抑制電磁干擾。數位控制振盪器整合於全數位鎖相迴路並搭配三角波形量變曲線產生器與和差積分調變器能建立全數位式展頻時脈產生器，有著易於晶片整合、較小面積以及較優的抗製程、電壓、溫度漂移的頻率可調範圍。在資料接受器端為了節省資料傳輸頻寬，需在幾十至幾百個位元時間回復突發傳入的大量資料。時脈與資料回復電路藉由使用閘式控制振盪器可在幾個位元時間內將回復的資料與時脈的相位校直來實現快速同步響應。 一個具低抖動、多相位差動輸出以及更為線性調整的數位控制振盪器被提出。此數位控制振盪器由四級差動延遲元件組成，可在較寬的頻率範圍擁有更為線性的調整。被提出的差動延遲元件設計主要由標準元件庫的邏輯元件以及電壓控制電容組成。利用和差積分調變實現抖動內插組合可改進數位控制振盪器的平均頻率解析度。在25億赫茲的載波上量測到的方均根抖動值與峰對峰抖動值分別為2.827皮秒與29皮秒。在1.2伏特供壓下消耗6毫瓦。實驗原型使用65奈米互補式金氧半導體製程，晶片面積為156×92平方微米。 展頻時脈的方法利用調變除頻除數達成在頻譜上以合成頻率為中心做小部分頻率展延。因此，在特定頻率被發射出的峰值能量被降低而能減輕電磁干擾。被提出的全數位式展頻時脈產生器以累加器為主的全數位鎖相迴路搭配和差積分條便器構成，並參考V-by-One顯示介面規格設計。全數位鎖相迴路用於合成三組頻段(2376百萬赫茲、740百萬赫茲及594百萬赫茲)搭配除頻器可滿足V-by-One顯示介面從62.5百萬赫茲到2376百萬赫茲的規格要求。從SIMULINK行為模擬顯示被抑制的電磁干擾值在2376百萬赫茲、740百萬赫茲以及594百萬赫茲的頻段上分別為19.95分貝、13.99分貝以及14.65分貝。使用40奈米互補式金氧半導體製程，此展頻時脈產生器的數位合成面積與在0.9伏特供壓下的功率消耗分別為4230平方微米與0.72毫瓦。使用28奈米互補式金氧半導體製程，應用於此展頻時脈產生器的頻段可選式數位控制振盪器的使用面積為1961平方微米以及在0.9伏特供壓下消耗3.34毫瓦。 一個突發模式時脈與資料回復電路應用於每秒百億位元被動式光通訊網路被提出。此電路的設計問題提出包含避免閘式控制振盪器的頻率不匹配、抖動容忍能力、較短鎖定時間以及能源效益的關切。此被提出的突發模式時脈與資料回復電路可在資料閘控階段與相位追鎖模式之間重新裝配以達成瞬間的相位鎖定且具備抖動抑制能力。鎖定頻率偵測器可確保一開始在頻率鎖定階段的準確度到百分之0.01875的誤差內。而被提出的具選擇性閘式壓控振盪器可傳遞輸入資料相位邊緣到閘式壓控振盪器的合適控制階級，使此一階級的時脈相位邊緣最為靠近輸入資料的相位邊緣。當此具選擇性閘式壓控振盪器穩定之後，輸入資料的相位轉折邊緣將與此選擇性閘式壓控振盪器在五分之一的輸出時脈相位校直。經過資料閘控過程之後，此突發模式時脈與資料回復電路重新裝配成一個二階傳統式時脈與資料回復電路，用於抑制輸入資料的抖動而不會遲滯鎖定行為。此突發模式時脈與資料回復電路藉由包含具選擇性閘式壓控振盪器操作在五分之一的資料速率且實現一比五同步解多工，可達成1.24皮焦耳每位元的高能源使用效率。在百億位元傳輸速率的資料上加入4百萬赫茲0.22峰對峰值單位長度的抖動量，此回復時脈的抖動在20億赫茲頻率上的方均根值為2.94皮秒。此實作模型使用55奈米互補式金氧半導體製程，核心面積只佔有0.03平方毫米。其消耗功率在1伏特供壓下為12.4毫瓦。

In modern times, the process technology node has advanced toward small feature size with low power consumption and high operation speed to per the demand on the enormous amount of data computation and communication among individual system-on-chip (SoC). The high-speed interface specifications have evolved toward multi-Gbps data rate as well as low-jitter and energy-efficient (~1pJ/bit) concerns. The transmitter (TX) utilizes spread-spectrum clock generator for the purpose of suppressing the electro-magnetic interference (EMI). The digitally-controlled oscillator (DCO) merged in the all-digital phase-locked loop (ADPLL) combining the triangular profile generator and ΣΔ modulator can build the all-digital spread-spectrum clock generator (SSCG) for the purpose of suppressing the electro-magnetic interference (EMI) with the advantages of the ease of chip integration, small feature size and PVT-tolerant frequency tuning range. For the receiver (RX), the burst-in data needs to be recovered within tens to hundreds of bit-times to save the bandwidth usage so that the big data can be transferred accordingly. By employing the gated-oscillator within the clock and data recovery (CDR) circuit, the recovered data and clock’s phases can be aligned within a few of bit-times to realize fast phase synchronization response. A low-jitter digitally-controlled oscillator (DCO) with multi-phase differential outputs and good linearity is presented. The DCO is composed of four differential delay cells, and can achieve linear tuning over a wide frequency range. The proposed fully differential delay cell comprises logic cells in standard library and varactors. The dithering scheme employing the ΣΔ modulation can enhance the average DCO’s frequency resolution. The measured rms jitter and pk-pk jitter from 2.5GHz carrier are 2.827ps and 29ps respectively. The power consumption is 6mW from a 1.2V supply. An experimental prototype is designed using 65nm CMOS technology, and the chip area is 156μm×92μm2. Spread-spectrum clocking method modulates the divider ration to spread the synthesized clock’s center frequency over a small portion on the spectrum. Therefore, the emitted peak energy at the discrete synthesized frequency can be reduced to alleviate the EMI effect. Through an accumulator-based ADPLL using ΣΔ modulator, the proposed all-digital SSCG can be built. The proposed SSCG uses V-by-One display specification for reference. The ADPLL can synthesize the three frequency bands (2376MHz, 740MHz, and 594MHz) accompanied with dividers to cover from 62.5MHz to 2376MHz frequency bands requirement. The SIMULINK behavioral simulation results show that the suppressed EMI amounts are 19.95dB, 13.99dB, and 14.65dB for the 2376MHz, 740MHz, and 594MHz frequency, respectively. The synthesized area and power of the SSCG’s digital components are 4230μm2 and 0.72mW from 0.9V supply in the 40nm CMOS process node. The band-selection DCO merged in this SSCG occupies area of 1961μm2 and dissipates 3.34mW from 0.9V supply in the 28nm CMOS process node. A burst mode clock and data recovery (BMCDR) circuit for 10Gbps passive optical network (10G-PON) is presented. The design issues including the prevention of the gated-oscillator’s frequency mismatch, the jitter tolerance ability, the short lock-in time and energy-efficient concern have been addressed. The proposed BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneously phase-locked with jitter suppression capability. The lock detector can guarantee the frequency accuracy of 0.01875% in the frequency initialization locked state. The proposed selectively gating voltage controlled oscillator (SGVCO) can pass the input data edge to the proper gating stage of the SGVCO that has the closest transition phases with it. When the SGVCO is settled, the input data transition edges are aligned with the SGVCO’s output phases at 1/5-rate of input data. After data gating process, the proposed BMCDR reconfigures as a 2nd-order conventional CDR loop to suppress input stressed data without retarding the locking behavior. By incorporating selectively gating VCO (SGVCO), the BMCDR can operate at 1/5-rate and accomplishes 1:5 demultiplexing with a high energy efficiency of 1.24pJ/bit. With a 4MHz, 0.22UIpp jitter stressed input data at 10Gbps, the recovered clock jitter at 2GHz is 2.94psrms. The prototype is fabricated using 55nm CMOS technology. The core area is 0.03mm2 only. It dissipates 12.4mW from 1V supply.